systemverilog packed struct assignment

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SystemVerilog Struct and Union – for Designers too

SystemVerilog struct (ure) and union are very similar to their C programming counterparts, so you may already have a good idea of how they work. But have you tried using them in your RTL design? When used effectively, they can simplify your code and save a lot of typing. Recently, I tried incorporating SystemVerilog struct and union in new ways that I had not done before with surprisingly (or not surprisingly?) good effect. In this post I would like to share with you some tips on how you can also use them in your RTL design.

What is a SystemVerilog Struct (ure)?

A SystemVerilog struct is a way to group several data types. The entire group can be referenced as a whole, or the individual data type can be referenced by name. It is handy in RTL coding when you have a collection of signals you need to pass around the design together, but want to retain the readability and accessibility of each separate signal.

When used in RTL code, a packed SystemVerilog struct is the most useful. A packed struct is treated as a single vector, and each data type in the structure is represented as a bit field. The entire structure is then packed together in memory without gaps. Only packed data types and integer data types are allowed in a packed struct. Because it is defined as a vector, the entire structure can also be used as a whole with arithmetic and logical operators.

An unpacked SystemVerilog struct, on the other hand, does not define a packing of the data types. It is tool-dependent how the structure is packed in memory. Unpacked struct probably will not synthesize by your synthesis tool, so I would avoid it in RTL code. It is, however, the default mode of a structure if the packed keyword is not used when defining the structure.

SystemVerilog struct is often defined with the typedef keyword to give the structure type a name so it can be more easily reused across multiple files. Here is an example:

What is a SystemVerilog Union?

A SystemVerilog union allows a single piece of storage to be represented different ways using different named member types. Because there is only a single storage, only one of the data types can be used at a time. Unions can also be packed and unpacked similarly to structures. Only packed data types and integer data types can be used in packed union. All members of a packed (and untagged, which I’ll get to later) union must be the same size. Like packed structures, packed union can be used as a whole with arithmetic and logical operators, and bit fields can be extracted like from a packed array.

A tagged union is a type-checked union. That means you can no longer write to the union using one member type, and read it back using another. Tagged union enforces type checking by inserting additional bits into the union to store how the union was initially accessed. Due to the added bits, and inability to freely refer to the same storage using different union members, I think this makes it less useful in RTL coding.

Take a look at the following example, where I expand the earlier SystemVerilog struct into a union to provide a different way to access that same piece of data.

Ways to Use SystemVerilog Struct in a Design

There are many ways to incorporate SystemVerilog struct into your RTL code. Here are some common usages.

Encapsulate Fields of a Complex Type

One of the simplest uses of a structure is to encapsulate signals that are commonly used together into a single unit that can be passed around the design more easily, like the opcode structure example above. It both simplifies the RTL code and makes it more readable. Simulators like Synopsys VCS will display the fields of a structure separately on a waveform, making the structure easily readable.

If you need to use the same structure in multiple modules, a tip is to put the definition of the structure (defined using typedef ) into a SystemVerilog package, then import the package into each RTL module that requires the definition. This way you will only need to define the structure once.

SystemVerilog Struct as a Module Port

A module port can have a SystemVerilog struct type, which makes it easy to pass the same bundle of signals into and out of multiple modules, and keep the same encapsulation throughout a design. For example a wide command bus between two modules with multiple fields can be grouped into a structure to simplify the RTL code, and to avoid having to manually decode the bits of the command bus when viewing it on a waveform (a major frustration!).

Using SystemVerilog Struct with Parameterized Data Type

A structure can be used effectively with modules that support parameterized data type. For example if a FIFO module supports parameterized data type, the entire structure can be passed into the FIFO with no further modification to the FIFO code.

Ways to Use SystemVerilog Union in a Design

Until very recently, I had not found a useful way to use a SystemVerilog union in RTL code. But I finally did in my last project! The best way to think about a SystemVerilog union is that it can give you alternative views of a common data structure. The packed union opcode example above has a “fields view” and a “dword view”, which can be referred to in different parts of a design depending on which is more convenient. For example, if the opcode needs to be buffered in a 64-bit buffer comprised of two 32-bit wide memories, then you can assign one dword from the “dword view” as the input to each memory, like this:

In my last project, I used a union this way to store a wide SystemVerilog struct into multiple 39-bit memories in parallel (32-bit data plus 7-bit SECDED encoding). The memories were divided this way such that each 32-bit dword can be individually protected by SECDED encoding so it is individually accessible by a CPU. I used a “dword view” of the union in a generate loop to feed the data into the SECDED encoders and memories. It eliminated alot of copying and pasting, and made the code much more concise!

SystemVerilog struct and union are handy constructs that can encapsulate data types and simplify your RTL code. They are most effective when the structure or union types can be used throughout a design, including as module ports, and with modules that support parameterized data types.

Do you have another novel way of using SystemVerilog struct and union? Leave a comment below!

• IEEE Standard for SystemVerilog 1800-2012

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4 thoughts on “SystemVerilog Struct and Union – for Designers too”

Love your posts!

I think you got something wrong in the first code example: Structs should have each element separated by semicolons, not commas.

i.e. typedef struct packed { my_opcode_t opcode; // 16-bit opcode, enumerated type my_dest_t dest; // 16-bit destination, enumerated type logic [15:0] opA; logic [15:0] opB; } my_opcode_struct_t;

Thanks Jonas for noticing the typo! You’re completely correct, I’ve fixed the code snippet above. The same code is correct in the download for this post (I did compile and test that one).

I noticed another typo in your second code example: my_opcode_struct_t opcode_s; “fields view” to the struct Should be: my_opcode_struct_t opcode_s; // “fields view” to the struct

Keep the helpful articles coming.

Ah yes, missed the slashes before the comments. Thanks!

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Structures and Unions in SV

Structure in systemverilog, significance of typedef in structures, structure example without typedef, structure example with typedef, types of structures, packed structures, packed structure example, unpacked structures, passing a structure in function or task, syntax for packed signed structure, unions in systemverilog, union example.

Working with SystemVerilog Structures by MBT

A note on testing, basic points.

• Project settings should say SystemVerilog 2005

Defining the struct

Example declaration that passes a structure both up and down:, to set fields in a structure-based wire:, alternative "setter":, to read fields out of a structure (wire or reg):, example instantiation of module that passes a structure both up and down:, using structs to pass data between synthesized and unsynthesized modules.

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systemverilog structure initialization with default = '1

Can someone shed light on what this SystemVerilog code should do:

Is this legal? I can't quite figure out the spec well enough to tell. This doesn't work right with Vivado, and I'm not sure why.

This works:

Thanks, Nachum

• system-verilog

2 Answers 2

Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns

my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000}; my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF};

Your version Vivado might not have implemented the default:'1 feature yet or it could be a bug in the simulator. Try to run the latest version.

Try default:16'hFFFF or default:-1 as possible work around.

One way to define complex structs can be explained with an example.

Lets be the following struct, which is a struct of integer arrays and a sub-struct called: AXI_PRM_STRCT

That complex struct can be initialized with literals in the following way:

There is other ways to init with literals

• \$\begingroup\$ The example is very nice, but where is the {default:'1} that was asked about? \$\endgroup\$ –  G Eitan Commented Jun 10, 2022 at 6:47

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Understanding SystemVerilog Structures Data Type

If you are delving into the world of circuit design, you might have heard of SystemVerilog structures data type. Structures provide an efficient way to organize and store complex data types. In this article, we will dive into the details of SystemVerilog structures, including the difference between unpacked and packed structures, and how to assign values to them.

Unpacked Structures

Unpacked structures are used to define a group of variables that have different data types. You can think of them as a collection of variables that are grouped together under a common name. Here is an example of an unpacked structure in SystemVerilog:

In this example, we have defined a structure called myStruct that contains three variables: data1 , data2 , and enable . The variable data1 is an 8-bit logic variable, data2 is a 16-bit logic variable, and enable is a single bit variable.

Packed Structures

Packed structures in SystemVerilog allow you to organize data into a single vector, which can then be divided into subfields. To declare a packed structure, you use the packed keyword, which tells the compiler to allocate the subfields in a contiguous block of memory.

Here's an example of a packed structure with two subfields:

In this example, myPackedStruct contains two subfields: subfield1 and subfield2 . The packed keyword tells the compiler to allocate these subfields in a single 16-bit vector. subfield1 occupies the 8 most significant bits, and subfield2 occupies the 8 least significant bits.

You can use arithmetic and logical operators with packed structures just as you would with individual variables. For example, you can add two packed structures together:

It's worth noting that you can also declare a packed structure as struct packed signed , which allows you to use the structure as a signed vector. Here's an example:

In this example, mySignedPackedStruct is declared as a struct packed signed with two subfields. This allows you to treat the entire packed structure as a signed vector, which can be useful in certain situations.

Assigning to Structures

You can assign values to structures just like you would assign values to individual variables. Here is an example:

In this example, we assign the value 01100100 to data1 , the value A1B2 to data2 , and the value 1 to enable .

You can also assign values to structures using the curly brace syntax. Here is an example:

In this example, we assign the same values to myPackedStruct using the curly brace syntax.

In conclusion, SystemVerilog structures provide an efficient way to organize and store complex data types. You can use either unpacked or packed structures, depending on your needs. Assigning values to structures is straightforward and can be done using either the dot syntax or the curly brace syntax. We hope this article has helped you understand SystemVerilog structures and how to use them in your circuit designs. Happy sailing!

Verification Guide

Packed and Unpacked array

Packed and unpacked array in systemverilog.

Table of Contents

• The term packed array is used to refer to the dimensions declared before the data identifier name
• The term unpacked array is used to refer to the dimensions declared after the data identifier name

Packed array

• Packed arrays can be of single bit data types (reg, logic, bit), enumerated types, and recursively packed arrays and packed structures
• Vector: A vector is a multi-bit data object of reg/logic/bit declared by specifying a range
• Scalar: Scalar is 1-bit data object of reg/logic/bit declared without specifying a range
• A packed array is a mechanism for subdividing a vector into sub-fields, which can be conveniently accessed as array elements.
• A packed array is guaranteed to be represented as a contiguous set of bits.

Packed array example

The below diagram shows storing packed array as a  contiguous set of bits.

UnPacked array

• Unpacked arrays can be of any data type.
• Unpacked arrays shall be declared by specifying the element ranges after the identifier name.
• An unpacked array may or may not be so represented as a  contiguous set of bits.

Unpacked array example

Below diagram shows storing unpacked array as a  non-contiguous set of bits.

❮ Previous Next ❯

SystemVerilog Packed Arrays

There are two types of arrays in SystemVerilog - packed and unpacked arrays.

A packed array is used to refer to dimensions declared before the variable name.

A packed array is guaranteed to be represented as a contiguous set of bits. They can be made of only the single bit data types like bit , logic , and other recursively packed arrays.

Single Dimensional Packed Arrays

A one-dimensional packed array is also called as a vector .

Multidimensional Packed Arrays

A multidimensional packed array is still a set of contiguous bits but are also segmented into smaller groups.

The code shown below declares a 2D packed array that occupies 32-bits or 4 bytes and iterates through the segments and prints its value.

Let us see a 3D packed array now.

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SystemVerilog: Question about array of packed struct

• Thread starter likewise
• Start date Jul 11, 2012
• Jul 11, 2012

Newbie level 5

Hello all, Suppose I have the following in SystemVerilog (intended to synthesize). typedef packed struct begin logic a; logic b; end mytype_t; mytype_t myarray [1:100]; Is it possible to set field 'a' of all array members with a single assignment? I understood from studying SV books it is possible to set a single dimension within a multidimensional array, and I would consider a field in a structure to be one dimension of my array. I would expect something like this: myarray.a <= 0; myarray[].a <= 0; myarray[0:100].a <= 0; Regards, Leon.  

• Jul 14, 2012

Advanced Member level 3

No, you can't select an array of selects. The most concise way to do what you want is foreach (myarray ) myarray .a <= 0;  

dave_59 said: No, you can't select an array of selects. The most concise way to do what you want is foreach (myarray ) myarray .a <= 0; Click to expand...

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Connecting hierarchical modules: struct vs interface in SystemVerilog

In SystemVerilog hierarchical modules can be connected by simple data types, complex data types (structs, unions, etc), or interfaces. The feature that I am interested in is aggregating all signals between two modules in one place which simplifies maintenance of the code.

For example in the following one change s_point's definition without changing the declarations of m1, m2, and top:

Alternatively, this could have been done using interfaces. However, I believe using structures are easier and they are supported by more CAD tools, and they don't need to be instantiated as is the case for interfaces (although one still has to declare them in the top module).

My question is if only aggregating signals is required (i.e. no interest in interface's task, functions, modports, generic interface, internal always blocks etc) for a synthesizable design, which one is preferred?

• system-verilog

interface is preferred.

A struct okay to use only when all the signals within the struct all follow the same port direction; input , output , or inout wire . It becomes challenging to use structs when driving directions become mixed. Mixed direction is a allow using the ref keyword, however the ref keyword is not supported by many synthesis tools, yet . inout cannot be used because logic is considered a variable, IEEE Std 1800-2012 § 6.5 Nets and variables. However, inout wire can be used to cast the struct as a net. The components of a stuct can not be assigned within an always-block and needs an assign statement instead; just like a regular wire .

An interface should be grouping signals where the port direction is not consistent. Tri-states need to be defined as wire and the variable types do not require explicit port direction when used in conjunction with always_{ff|comb|latch} . It should also be used if the signals are part of a protocol. This way assertions can be added and it can be connected to a classes for an UVM test-bench or other SVTB environment.

Use a sturct when only passing a explicit direction data type. Use an interface for passing shared signals.

Example Senario:

Imagine there is a collection of signals x , y ,& z , where module m_x drives x and reads y & z , module m_b drive y and reads x & z , and module m_z drives z and reads x & y . Each signals have only one driver and always_ff can be used to guarantee this.

If we try adding a bidirectional tri-state bus , to the mix then the struct cannot be used. A wire resolves conflicting drivers while logic / reg clobber and keep the scheduler running.

Sample code:

Using struct using ref (no tri-state allowed):

Using struct using inout wire (nets must be driven with assign , loses single driver guarantee):

Using interface (with tri-state):

Running code: http://www.edaplayground.com/s/6/1150

• 1 One correction: you can use a struct data type for a wire and therefore connect to an inout port, but you still have the problem of only one direction spec per struct port. –  dave_59 Commented Jan 24, 2014 at 5:25
• @dave_59 Good catch I missed that from "6.7.1 Net declarations with built-in net types", I've updated my answer. –  Greg Commented Jan 24, 2014 at 17:19
• Thank you for your input. Assertions and having multi-directional signals in one single interface is certainly a good reason to use interfaces as opposed to the alternative which is defining one struct for inputs and one for outputs. In my experience however, the synthesis tools still require you to explicitly define modports for signal directions. Tri-states and inout ports are not that common, at least in my experience. But another reason that made me use interfaces was the ability to parametrize them, which is not the case with simple structures. –  Ari Commented Jan 24, 2014 at 22:12
• @Ari, if this answer was useful, then please click accept. If not, what additional information is needed? –  Greg Commented Dec 4, 2014 at 16:58
• @Greg: I up-voted your answer, but I don't quiet agree that interfaces are always preferred. Many common designs don't have bi-dir or tri signals. For your interface-based design to be synthesizable, you should define modports. If the design doesn't structurally need aggregation of input/output signals why not just have inputs in one struct and outputs in another to get a less complicated code which is supported by most synthesis tools (interfaces are not fully supported on some yet). In my experience interfaces are mostly useful when implementing complicated bus transactions. –  Ari Commented Dec 4, 2014 at 18:36

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