asynchronous sar adc thesis

A study of SAR ADC and implementation of 10-bit asynchronous design

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Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC’s analog components – comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 µm. Design’s noise and power are presented as a breakdown among components.

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This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC

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This project is about the design process of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using 45nm CMOS technology. SAR ADCs are attractive circuits for applications that require low power with medium resolution and medium speed like in computing-in-memory cores for AI applications and in sensors for biomedical applications. The asynchronous architecture allow the ADC to operate without the need for an oversampled clock reducing the design complexities associated with higher frequencies. The top-level block diagram of the asynchronous SAR ADC is shown below, along with the timing diagram of the important signals.

1) Internal Clock Generator

The internal clock generator is the block responsible for providing the rest of the system with the clock signals to operate. This block produces 2 output signals, “clk_sample” and “clk_sar”, and receives 3 inputs “clk_ext”, “Ready”, and “EOC”.

2) Bootstrapped Sample-And-Hold Switches

The sample-and-hold circuit is basically a switch that captures the value of an analog signal at a certain moment and holds it constant for a certain amount of time. The bootstrapped switch help mitigate some of the switch non-idealities by keeping the switch’s VGS fixed during the sampling phase.

3) Capacitive DAC

The capacitive DAC uses charge redistribution to convert the digital code coming from the SAR logic into the corresponding analog voltage level to be compared by the comparator.

4) Dynamic Comparator

The comparator’s function is to compare the analog input levels coming from the DAC and to produce a digital output bit (either high or low) representing the result of the comparison. A high-speed low-power strongarm comparator is used.

5) SAR Logic

The SAR logic generates the digital code for the DAC in each comparison stage. At the end of the conversion cycle, the final digital code is outputted by an output register. The flipflops used are TSPC flipflops with asynchronous set and reset inputs.

* Analysis & Results:

Key References:

[1] O. Kardonik, "A study of SAR ADC and implementation of 10-bit asynchronous design," M.S. Thesis, Department of Electrical and Computer Engineering, University of Texas at Austin, 2013.

[2] P. J. A. Harpe et al., "A 26 uW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios," IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, July 2011.

[3] M. Al-Qadasi, A. Alshehri, A. S. Almansouri, T. Al-Attar, and H. Fariborzi, "A High Speed Dynamic StrongARM Latch Comparator," 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, 2018, pp. 540-541.

[4] M. Dessouky and A. Kaiser, "Very low-voltage digital-audio Δ∑ modulator with 88-dB dynamic range using local switch bootstrapping," IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 349-355, March 2001.

For more info, check the project's report & ppt: https://github.com/muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC/blob/main/%5BReport%5D%20Design%20of%20a%20Low-Power%20Asynchronous%20SAR%20ADC%20in%2045%20nm%20CMOS%20Technology.pdf

https://github.com/muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC/blob/main/%5BPPT%5D%20Design%20of%20a%20Low-Power%20Asynchronous%20SAR%20ADC%20in%2045%20nm%20CMOS%20Technology.pdf

My project on google drive: https://drive.google.com/drive/folders/1zEzuneabBBtgcV0V-nYb4Kvp_cLarDpZ?usp=sharing

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A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

Deeksha verma.

1 Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea; ude.ukks@72ahskeed (D.V.); ude.ukks@8961maruhk (K.S.); ude.ukks@jsk701nus (S.J.K.); ude.ukks@5101arah (Y.G.P.); rk.ca.tsiak@retpar (S.-S.Y.); ude.ukks@gnawhk (K.C.H.); ude.ukks@90gnay (Y.Y.)

Khuram Shehzad

2 SKAIChips Co., Ltd., Suwon 16419, Korea

Sung Jin Kim

Young gun pu, sang-sun yoo, keum cheol hwang, youngoo yang, kang-yoon lee, associated data.

Not applicable.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

1. Introduction

For low-power applications, a Successive Approximation Register (SAR) analog-to-digital converter (ADC) is a good choice to obtain successive digital code from an analog input by using the binary search algorithm. Due to its simplicity and power efficiency, SAR ADC is more popular and favorable for comparison with other types of ADCs [ 1 , 2 , 3 ]. Traditionally, pipeline ADCs have been frequently used for high-speed and medium-resolution data converters. However, the down-scaling of CMOS technologies and reduction in the power supply voltages arouses some significant obstacles for the power-efficient design of pipeline ADCs, because pipeline ADCs have need for high-gain operational amplifiers, which increases the power consumption of pipeline ADCs. In addition to this, it also degrades the swing of amplifiers, which results in the reduction of the Signal-to-Noise Ratio (SNR) for the provided sampling capacitance value. Additionally, the operational amplifier needs to have high DC gain, which lowers the power efficiency because of the low output resistance from short-channel-length devices. On the other hand, SAR ADCs abolish the requirement for an operational amplifier and can attain magnificent power efficiency [ 4 , 5 ]. According to the present trend, SAR ADC provides a sampling speed of several tens of MS/s for medium resolution, which permits the design of low-power and high-performance ADCs. SAR ADCs also have the characteristic of power dissipation being directly related to the sampling rate. These features of SAR ADCs make them the ideal candidate for many applications, such as data signal acquisition, battery management systems, pen digitizers, etc. The simple concept of the SAR ADC is that the analog input will be held by the sample and then be compared with the reference voltage of the ADC, which is an output of the DAC. A stable reference voltage is required for high-resolution ADCs. For SAR ADCs, static bias current is not required in the design of the dynamic comparator [ 6 , 7 ]; hence, the overall power consumption of SAR ADC scales with the sampling rate.

In the SAR ADC, the analog input signal is compared with the reference voltage by a comparator. This reference voltage should be stable and independent of the environmental condition for the stable analog-to-digital conversion [ 8 ]. The reference voltage can also be generated by the supply voltage, but it suffers around ±10% of variation [ 9 ]; hence, SAR ADC requires a high-precision reference voltage generated by an on-chip bandgap reference voltage generator circuit [ 10 ]. The reference voltage cannot vary with the operating conditions, but it can change within the small range of process, voltage, and temperature (PVT) variations [ 8 , 11 , 12 ]. Furthermore, parasitic inductance affects the reference voltage line and degrades the overall ADC performance when the reference voltage is generated off-chip. In order to achieve the targeted SAR ADC performance, it requires an on-chip reference voltage generator circuit.

In this work, we present a power-efficient single-ended asynchronous SAR ADC implemented in 130 nm CMOS technology. The proposed dual-path bootstrap switch reduces the sampling nonlinearity. The VCM-based switching sequence is proposed, which reduces the capacitive DAC total capacitance by half due to the additional reference of VCM. For high speed and power efficiency, we implemented a two-stage dynamic latch comparator. To overcome the speed limitation, which is caused by the capacitive DAC settling, an on-chip bandgap reference voltage generator has been implemented. The design details and topology of a dual-path bootstrap switch, capacitive DAC, a two-stage dynamic comparator, asynchronous SAR logic, and an error amplifier-based bandgap reference voltage generator that satisfies the performance requirements are further discussed in detail.

The proposed single-ended asynchronous SAR ADC architecture is described in Section 2 . The sub-blocks of the proposed asynchronous ADC, such as dual-path bootstrap switching, VCM-based capacitive DAC switching, two-stage dynamic latch comparator, asynchronous SAR logic, and error-amplifier-based bandgap reference voltage generator are described in Section 3 , and the measurement results are presented in Section 4 . Finally, we conclude the paper in Section 5 .

2. Proposed ADC Architecture

The proposed single-ended asynchronous SAR ADC topology is designed and fabricated for a 10-bit resolution with a sampling speed of 1 MS/s, and the architecture is presented in Figure 1 . The proposed SAR ADC contains a binary weighted capacitive DAC, a bootstrap switch, dynamic comparator, asynchronous SAR logic with an internal comparator clock generator, and a bandgap reference generator. A dual-path bootstrap switch is presented that overcomes the sampling nonlinearity. The VCM-based switching sequence is proposed, which reduces the capacitive DAC’s total capacitance by half due to the additional reference of VCM. Owing not only to the reduced capacitance, but also to the reduced switching step size as well as the removed switching-back operation, the VCM-based CDAC switching achieves excellent energy efficiency. The capacitive DAC is controlled by the digital output code, which is stored by asynchronous SAR logic and the decision made by the comparator. In the proposed single-ended asynchronous SAR ADC, a reference voltage of 0.6 V is generated by the error amplifier (EA)-based bandgap reference voltage generator. The 10-bit capacitive DAC provides the reference voltage DACP to the one input of the comparator, and the other input comparator has common-mode voltage (VCM). The sampling and hold operation is conducted by the sampling switch and capacitive DAC capacitors. The sampling signal, DACP<9:0>, CCLK, and SSAM are the control signals generated from the asynchronous SAR logic. The CCLK signal is provided to the comparator for the fast comparison of the comparator. For high speed and power efficiency, we implemented a two-stage dynamic latch comparator. In addition to this, for practical use, we implemented an on-chip bandgap reference voltage generator that provides better stability and reduced offset voltage distribution.

The proposed block diagram of the asynchronous SAR ADC with an EA-based bandgap reference voltage generator circuit.

3. Circuit Implementation

3.1. bootstrap switching.

Nowadays, for linear sampling, a bootstrap switch is frequently used, and its non-idealities have become pronounced; thus, its linearity is seriously degrading. Several techniques have been used to improve the performance of the bootstrap switch, such as modifying the circuit network or incorporating fast-turn-on circuits [ 13 ]. In Figure 2 , we propose a technique to improve the linearity of the bootstrap switch. Ideally, to achieve the constant switch on-conductance, the Vgs of the sampling transistor M10 is independent of and constant with the input. The proposed technique integrates the dual-path bootstrap switch to improve the sampling nonlinearity, and operates at the sampling rate of 1 MS/s, with a 50% duty cycle and peak-to-peak voltage of 600 mV, as shown in Figure 2 . This technique creates two paths for the signal; one is the main path, which contains M2 and C2, and the other is an auxiliary path, which contains M1 and C1. In the auxiliary path, the PMOS transistor’s M1, M2, and M4’s bulk terminals are connected to the V X node, which prevents forward biasing. By the proposed dual-path bootstrap switching technique, the nonlinear capacitance drives through the auxiliary path, while the gate of the sampling switch propagates the input signal, and hence the nonlinear capacitance is not directly being loaded into the main path. In this way, we can maximize the drive strength and signal linearity by independently optimizing the auxiliary path and the main path. The formula for voltage transfer to V g from VIN and its phase are expressed as follows:

where R 4 = 1/G4, G4 is the on conductance of transistor M4, and Cg is the gate capacitance of transistor M10. By the proposed bootstrap switch, G4 is more linear because, instead of the supply voltage VDD, the bulk of M4 is connected to the nonlinear voltage V X . Therefore, the square root of the error of nonlinear voltage V X is directly proportional to G4. Hence, to improve the nonlinearity, the nonlinear voltage V X goes through the bulk of M4, and nonlinear parasitic capacitance from the main path is removed by C2.

The schematic of the proposed bootstrap switch.

3.2. Capacitive DAC

Various circuit techniques could further enhance the low power advantage of SAR ADCs. A large amount of research has been conducted to save the CDAC’s switching power consumption. Unlike the traditional SAR ADC architecture with two voltage references, the VCM-based switching scheme proposed could reduce the total capacitance of the CDAC by half due to the additional reference of VCM. It does not only reduce the overall CDAC capacitance, but also reduces the switching step size. With the removed switching-back operation, the VCM-based CDAC switching could achieve excellent energy efficiency and become popular for low-power designs. One drawback of the VCM-based switching scheme might be the difficulty in designing low-resistance switches for VCM. The monotonic switching technique can eliminate the need for VCM by the asymmetric CDAC switching, but this scheme has a varying common-level problem [ 14 , 15 ]. The energy-saving switching technique could implement VCM-based-like switching behavior without utilizing VCM by splitting each capacitor in half. The improved process controllability of advanced CMOS technologies also contributed to reducing the CDAC switching power consumption by decreasing the minimum unit capacitor values without the need for a dedicated process for capacitor implementation.

The proposed CDAC switching with the binary weighted array used in the single-ended SAR ADC is depicted in Figure 3 . In the sampling phase, the bottom plates of all capacitors are connected to the VCM and the top plates are connected to the VIN. Thus, the input voltage is sampled on the binary weighted capacitor array, and we obtain the first signed bit without consuming any switching energy. Depending on the first signed bit, the next conversion cycle is either charged to VDD or discharged to VSS from VCM. Hence, the MSB capacitor is not required in the proposed switching scheme. The sensitivity due to the capacitor mismatch, dynamic, and static performance of the proposed capacitive DAC switching scheme is checked based upon the behavioral simulation in MATLAB. The fast Fourier transform (FFT) spectrum of the behavioral model-level simulation is evaluated in MATLAB ® for the proposed switching architecture with 1% unit capacitor mismatch, as shown in Figure 4 . The static performance metrics, differential non-linearity (DNL), and the integral non-linearity (INL) of the proposed switching with 1% unit capacitor mismatch are shown in Figure 5 a,b respectively.

The proposed 3-bit switching method for single-input SAR ADC.

Dynamic performance of proposed switching with 1% unit capacitor mismatch.

Static performance of the proposed switching with 1% unit capacitor mismatch. ( a ) DNL; ( b ) INL.

Figure 6 shows the output of the capacitive DAC (DACP) settling of input signals according to the clock signal. An end-of-conversion (EOC) signal will be generated after the completion of the conversion cycle based on the asynchronous SAR logic.

Simulation result of capacitive DAC.

3.3. Two-Stage Dynamic Comparator

In the proposed two-stage dynamic latched comparator, two inverters are added to make the V i node’s voltage strong by providing a higher regeneration speed, as shown in Figure 7 . The proposed architecture of the two-stage dynamic latch comparator provides high speed and power efficiency, and lowers the input-referred offset compared with conventional comparator architecture [ 16 , 17 , 18 ]. When the clock signal CCLK is turned off, the PMOS transistors M11 and M12 are on, then the V i nodes are charged to VDD, and VB i nodes are discharged to VSS during the reset phase. Consequently, there is no static power dissipation and static path due to charge sharing, and no DC flows in the static state of the proposed comparator. The NMOS transistors M9 and M10 drain, and output nodes charge to VDD, while the PMOS transistors of the regeneration stage turn on, and the VB i nodes discharge to VSS.

Transistor-level schematic of the dynamic comparator.

In the evaluation phase, when the clock signal CCLK increases, the V i nodes discharge to VSS depending on the input voltage through the input transistors M13 and M14, and the tail transistor M15. The VB i nodes are charged from VSS to VDD, while the V i nodes are discharged to VSS in the evaluation phase. Other transistors will be turned on when the NMOS transistors M9 and M10 are turned on in the second stage and either of the VBi nodes reaches the threshold voltage V th . Consequently, the latch is activated and regenerates the digital voltage at the output.

3.4. Asynchronous SAR Logic and Comparator Clock Generator

To achieve faster bit conversion with an efficient time sequence, asynchronous SAR ADC is more popular [ 19 , 20 ]. Asynchronous SAR logic with an internally generated clock avoids the requirement for the high-frequency external clock, as all conversions are carried out in a single clock cycle. Asynchronous SAR control logic is implemented for a shorter critical path.

A clock generator for SAR control logic is proposed, as shown in Figure 8 a. The asynchronous clock generator consists of a delay cell, variable delay, an edge counter, delay adjust block, and logic gates. VCOMP or VCOMN are low, which allows VI to decrease after the decision of the comparator. Then, after the variable delay, VO is also low, which makes the CCLK decrease, and the SAR logic controller is triggered. The comparator starts the comparison when the reset of the comparator is completed, and VI, VO, and CCLK increase. To maximize the sampling period of conversion and to adjust the time delay, the delay adjust block and counter are used in feedback.

( a ) Block diagram of the clock generator; ( b ) timing diagram of the clock generator.

CCLK provides the reset time of the comparator and more time for DAC settling, as shown in Figure 8 b. The proposed clock generator eliminates the memory effect in the comparator and speeds up the bit conversion. Hence, it also helps to improve the ADC robustness. The timing diagram of the proposed clock generator is shown in Figure 8 b. The comparator’s decision time and reset time are represented as T1 and T2, respectively. D1 and D2 are the delay time, and unequal D1 and D2 can be obtained by the variable delay cell, as depicted in Figure 9 . The variable delay cell is composed of an inverter array, implemented to achieve the desired variable delay. The arrangement of the inverter array leads the delay D1 to be small for the falling edge from VI to VO and delay D2 to be large for the rising edge.

Schematic of variable delay cell.

3.5. Error Amplifier-Based Bandgap Reference Voltage Generator

Reference voltage generators are required to stabilize the overall PVT variation, and also need to be implemented without modifying the fabrication process [ 21 , 22 , 23 ]. The bandgap reference voltage generator (BGR) is a popular reference voltage generator that successfully achieves the requirements [ 24 , 25 ]. Low power and low voltage operation are the characteristics of reference voltage generators. The error amplifier feedback keeps the same voltage level at both inputs of EA, and R3 generates the voltage difference between the two BJTs, as represented in Figure 10 . A Soft-Start circuit is added to the output; when the power signal is high, a current starts to flow through the PMOSs, M11, M12, and M13 connected in diode fashion. To prevent the BGR peak voltage, it slowly charges the capacitor C3, and the BGR output voltage rises. The output of the error amplifier controls the gate of transistors M1 and M3 so that the input voltages of the error amplifier are equal. The positive feedback and negative feedback improve the loop stability of the proposed error amplifier. A detailed schematic of the error amplifier-based BGR circuit is shown in Figure 11 a. VB1, VB2, and VB3 are the biasing voltages provided by the bias circuit to the cascaded error amplifier. We assume that the transistors M15–M18 and M23 are matched in terms of their aspect ratios, and the drain current of M18 is represented as:

Schematic of BGR.

( a ) Detailed schematic of the proposed error amplifier based bandgap reference voltage generator; ( b ) Proposed folded-Cascoded error amplifier with intentional positive and negative feedback loop.

Initially, V off caused the output offset current I off of the proposed error amplifier circuit shown in Figure 11 b. Between the feedback stage and cascade stage output, OUT triggers the two opposite currents. The offset currents I 18 and I 20 are the positive feedback path and negative feedback path, respectively, and act contrary to each other. Therefore, the output offset current I off is expressed as follows:

where V ov is the overdrive voltage; V ov = OUT − V TH and I 20 = g m V off /2. By carefully setting the overdrive voltage V ov and transconductance g m , we can alleviate the output offset current I off , as estimated by Equation (5). We assume that all transistors’ transconductance is the same; then Equation (5) can be expressed as:

Equation (6) represents that we can reduce the output offset current I off by adjusting the V ov22 to V ov16 + V off . This type of reduction in the output offset current I off can be achieved by inducing the intentional feedback loop in the proposed error amplifier. The Monte Carlo simulation of the proposed error amplifier-based bandgap reference voltage generator is depicted in Figure 12 . An on-chip voltage generator with a standard deviation of less than 1 LSB is used in the proposed ADC architecture.

Monte Carlo simulation result of error amplifier-based bandgap reference voltage generator.

4. Measurement Results

The proposed SAR ADC architecture with VBGR was implemented and tested with TSMC 130 nm CMOS technology. Figure 13 represents a die photograph of the asynchronous SAR ADC with VBGR. The measured dynamic performance of the ADC at 153.32 kHz and 450.19 kHz input frequencies with a sampling rate of 1 MS/s is presented in Figure 14 a,b, respectively. The proposed SAR ADC architecture achieved 9.49-bit ENOB and 58.88 dB SNDR with an input frequency of 153.32 kHz, as shown in Figure 14 a, and 8.94-bit ENOB and SNDR of 55.62 db with an input frequency of 450.19 kHz at 1 MS/s sampling speed, as shown in Figure 14 b.

Die photograph of the asynchronous SAR ADC with VBGR.

Measured dynamic performance at a sampling speed of 1 MS/s with the two different input frequencies: ( a ) 153.32 MHz input frequency; ( b ) 450.19 MHz input frequency.

To check the linearity or the static performance of the proposed SAR ADC, the measured DNL and INL results are presented in Figure 15 . The measured DNL and INL were −0.57/0.58 LSB and −0.72/0.55 LSB, respectively. The ENOB trend of the proposed ADC with an on-chip EA-based bandgap reference voltage generator is depicted in Figure 16 a,b, representing the power breakdown of the proposed EA-based bandgap reference voltage generator. Table 1 summarizes the performance of the proposed SAR ADC architecture and compares it with the other state-of-the-art SAR ADC architectures. The figure of Merit (FOM) is generally used to check the overall performance of ADC, and the FOM can be evaluated as below:

where the sampling rate is presented as F S , bandwidth of ADC is denoted as BW, and power consumed by the proposed ADC is represented as Power ADC . The proposed SAR ADC architecture achieved a FOM of 66.25 fJ/conv-step.

Measured static performance: ( a ) Differential non-linearity (DNL); ( b ) Integral non-linearity (INL).

( a ) Measured ENOB trend at different input frequencies with 1 MS/s sampling speed; ( b ) Power breakdown of proposed ADC.

Performance summary and comparison table.

5. Conclusions

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous SAR ADC with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance several, techniques have been proposed. A dual-path bootstrap switch is proposed to increase the linearity sampling. The VCM-based CDAC switching technique has been implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve the faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement for a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides stable reference voltages to the ADC for practical implementation. The measurement results of the proposed SAR ADC including an on-chip bandgap reference voltage generator showed an ENOB of 9.49 bits and SNDR of 58.88 dB with 1.2 V of power supply and operation with a sampling rate of 1 MS/s.

Acknowledgments

This paper was supported by Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) (P0012451, The Competency Development Program for Industry Specialist).

Funding Statement

This research received no external funding.

Author Contributions

Conceptualization, D.V. and K.S.; methodology, D.V.; software, D.V., K.S. and S.J.K.; validation, D.V. and K.S.; formal analysis, D.V. and K.S.; investigation, D.V. and K.S.; resources, D.V.; data curation, D.V. and K.S.; writing—original draft preparation, D.V. and K.-Y.L.; writing—review and editing, D.V., Y.G.P., S.-S.Y. and K.-Y.L.; visualization, D.V., K.S. and K.-Y.L.; supervision, K.C.H., Y.Y. and K.-Y.L.; project administration, K.-Y.L. All authors have read and agreed to the published version of the manuscript.

Institutional Review Board Statement

Informed consent statement, data availability statement, conflicts of interest.

The authors declare no conflict of interest.

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SAR ADCs Design and Calibration in Nano-scaled Technologies

The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Among various ADC architectures, successive-approximation-register (SAR) ADCs have received renewed interest from the design community due to their low hardware complexity and scaling-friendly property. However, the conventional SAR architecture has many limitations for high-speed, high-resolution applications. Many modified SAR architectures and hybrid SAR architectures have been reported to break the inherent constraints in the conventional SAR architecture. Loop-unrolled (LU) SAR ADCs have been recognized as a promising architecture for high-speed applications. However, mismatched comparator offsets introduce input-level dependent errors to the conversion result, which deteriorates the linearity and limits the resolution and the resolution of most reported SAR ADCs of this kind are limited to 6 bits. Also, for high-resolution SAR ADCs, the comparator noise specification is very stringent, which imposes a limitation on ADC speed and power-efficiency. Lastly, capacitor mismatch is an important limiting factor for SAR ADC linearity, and generally requires dedicated calibration to achieve efficient designs in terms of power and area. In this work, we investigate the impacts of offset mismatch, comparator noise and capacitor mismatch on high-speed SAR ADCs. An analytical model is proposed to estimate the resolution and predict the yield of LU-SAR ADCs with presence of comparator offset mismatch. A background calibration technique is proposed for resolving the comparator mismatch issue. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7-dB to 42.9-dB. The ADC consumes 640 μW from a 1.2 V supply with a Figure-of-Merit (FoM) of 37.5-fJ/conv-step. Moreover, the bit-wise impact of comparator noise is studied for LU-SAR ADCs. Lastly, an extended statistical element selection (SES) calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. Based on these techniques, a high-resolution, asynchronous SAR architecture employing multiple comparators with different speed and noise specifications to optimize speed and power efficiency. A 12-bit prototype ADC is fabricated in a 1P9M 65nm CMOS technology, and fits into an active area of 500 μm × 200 μm. At 125 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 64.4 dB and a spurious-free-dynamic-range (SFDR) of 75.1 dB at the Nyquist input frequency while consuming 1.7 mW from a 1.2 V supply. The resultant figure-of-merit (FoM) is 10.3 fJ/conv-step.

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• Doctor of Philosophy (PhD)

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Design Techniques for High-Performance SAR A/D Converters

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The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology.

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A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

• Published: 21 January 2021
• Volume 40 , pages 3125–3142, ( 2021 )

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• Mengying Hu 1 ,
• Jing Jin   ORCID: orcid.org/0000-0003-3584-5559 1 ,
• Yuekang Guo 1 ,
• Xiaoming Liu 1 &
• Jianjun Zhou 1  

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This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm \(^{2}\) area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.

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Acknowledgements

We would like to thank the Chinese National Nature Science Foundation (No. 61974092) for funding this research.

Chinese National Nature Science Foundation (No. 61974092)

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Center for Analog/RF Integrated Circuits (CARFIC), Department of Micro/Nano Electronics, Shanghai Jiao Tong University, Shanghai, 200240, China

Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu & Jianjun Zhou

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Hu, M., Jin, J., Guo, Y. et al. A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. Circuits Syst Signal Process 40 , 3125–3142 (2021). https://doi.org/10.1007/s00034-020-01643-z

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Received : 03 August 2020

Revised : 23 December 2020

Accepted : 24 December 2020

Published : 21 January 2021

Issue Date : July 2021

DOI : https://doi.org/10.1007/s00034-020-01643-z

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