assignment to vectors in verilog

HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL

New citation alert added.

This alert has been successfully added and will be sent to:

You will be notified whenever a record that you have chosen has been cited.

To manage your alert preferences, click on the button below.

New Citation Alert!

Please log in to your account

Information & Contributors

Bibliometrics & citations, view options, 1 introduction.

2 Related Works

3 presentation of the hdlruby language, 3.1 overview of the language, 3.2 an example of hdlruby code.

3.3 Implementing a Generic Multi-dimensional CNN with HDLRuby

3.3.1 overview of the cnn implementation., 3.3.2 the global network module..

3.3.3 The Abstract Description of a Layer.

3.3.4 the description of a dense layer., 3.3.5 the description of layers based on sliding windows..

3.3.6 The Descriptions of a Convolution Layer and a Pooling Layer.

4 Extending Ruby to HDLRuby

4.1 the basic constructs of the hdlruby language, 4.2 integrating the hardware expressions, 4.3 integrating the hierarchy, 4.4 integrating the statements.

4.5 Integrating the Declarations

4.6 names and access to hardware components.

4.7 Managing Namespaces

4.8 integrating inheritance, 4.9 integrating genericity and metaprogramming.

5 Processing HDLRuby Description

5.1 Building the HDLRuby RTL Tree

5.2 Converting the HDLRuby RTL Tree for Easy Translation to Other HDL

5.3 Generating the Verilog HDL Code

6 experiments.

7 Conclusion

Index terms.

Electronic design automation

Hardware description languages and compilation

Recommendations

Synthesizable standard cell fpga fabrics targetable by the verilog-to-routing cad flow.

In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA ...

Verilog HDL Synthesis: A Practical Primer

The verilog procedural interface for the verilog hardware description language.

The Verilog Procedural Interface is a new C programming interface for the Verilog Hardware Description Language. Different Verilog HDL based tools such as simulators, synthesizers, timing analyzers, and parsers could support this interface for ...

Information

Published in.

Association for Computing Machinery

New York, NY, United States

Journal Family

Publication history, check for updates, author tags.

• Register transfer level
• software language
• Research-article

Funding Sources

• Japanese Grants-in-Aid for Scientific Research

Contributors

Other metrics, bibliometrics, article metrics.

• 0 Total Citations
• 292 Total Downloads
• Downloads (Last 12 months) 225
• Downloads (Last 6 weeks) 73

View options

View or Download as a PDF file.

View online with eReader .

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Share this publication link.

Copying failed.

Share on social media

Affiliations, export citations.

• Please download or close your previous search result export first before starting a new bulk export. Preview is not available. By clicking download, a status dialog will open to start the export process. The process may take a few minutes but once it finishes a file will be downloadable from your browser. You may continue to browse the DL while the export process is in progress. Download
• Download citation
• Copy citation

We are preparing your search results for download ...

We will inform you here when the file is ready.

Your file of search results citations is now ready.

Your search export query has expired. Please try again.

Verilog Vectors and Arrays

Welcome back to my series covering mathematics and algorithms with FPGAs. In this part, we dig into vectors and arrays, including slicing, configurable widths, for loops, and bit and byte ordering. New to the series? Start with Numbers in Verilog .

Share your thoughts with @WillFlux on Mastodon or Twitter . If you like what I do, sponsor me . 🙏

Series Outline

• Numbers in Verilog - introduction to numbers in Verilog
• Vectors and Arrays (this post) - working with Verilog vectors and arrays
• Multiplication with DSPs - efficient multiplication with FPGA DSPs
• Fixed-Point Numbers in Verilog - precision without complexity
• Division in Verilog - divided we stand
• More maths to follow

What is a Vector?

A quick recap from Numbers in Verilog :

By default, a Verilog register or wire is 1 bit wide. This is a scalar :

A scalar can only hold 0 or 1 1 .

We need a vector to hold something larger.

A vector is declared like this: type [upper:lower] name;

a , b , and c are vectors:

• Wire a handles 0-63 inclusive (2 6 is 64).
• Register b handles 0-255 inclusive (2 8 is 256).
• Logic c handles 0-4095 inclusive (2 12 is 4096).

With that recap out of the way, let’s look at some things we can do with vectors.

Slicing Vectors

You select an individual bit using its index; for example:

You select a subset by specifying the start and end bits:

You can also use the concat operator {} to select bits from vectors. The following example is equivalent to the one above:

Rather than specify an end bit, you can specify a width with - and + .

These three assignments all select the same four bits:

ProTip: The start bit can be a variable, but not the width.

Loss of Sign

With signed variables, using slices will make the value unsigned, even if you select the whole range!

However, you can force a variable to be signed with the $signed system function:

Produces the following:

$signed is no panacea: sign extension can still catch you out.

Configurable Widths

Avoid hard-coding vector widths; it limits your design flexibility.

Parameters provide a simple way to configure vector widths:

The width of a vector often depends on another parameter, so calculating it yourself isn’t ideal.

Imagine you’re creating a game engine where the number of sprites is configurable:

Changing the sprite count will break the design if we hardcode the width.

Verilog 2005 introduced $clog2 to handle this.

Calculating Widths

The $clog2 function returns the ceiling of the logarithm to base 2.

For example, $clog2(10) = 4 because 2 3 < 10 ≤ 2 4 .

If you need to handle N things (such as sprites or memory locations), then $clog2(N) will tell you how wide your vector needs to be:

$clog2 is handy, but you need to be careful.

If you’re specifying a maximum value (rather than a count), it doesn’t do what you want:

$clog2 returns ‘8’, giving a voltage range of 0-255 inclusive. 256 is out of range.

If you’re specifying a maximum value, you need to add one to the value passed to $clog2 :

This problem is often hidden because it doesn’t occur if your parameter isn’t a power of 2. For example, if you specify ‘240’ as your MAX_VOLTAGE , you won’t see any issues. Later, you increase MAX_VOLTAGE to ‘256’, and the design has a subtle bug.

A Bit Significant

Earlier, we said a vector was declared like this: type [upper:lower] name;

A more general definition is: type [msb_index:lsb_index] name;

Where msb_index is the most significant bit index, and lsb_index is the least significant bit index.

The usual way of declaring vectors has the least significant bit at the lowest index (LSB first):

The most significant bit of a is stored in a[5] and that of b in b[11] .

Alternatively, we can declare vectors with the most significant bit at the lowest index (MSB first):

The most significant bit of c is stored in c[0] and that of d in d[0] .

Switching Ends

MSB-first vectors are comparatively rare in Verilog. However, some hardware interfaces send the most significant bit first, for example, I 2 C.

Say you’ve got an MSB first byte from I 2 C and want to convert it to LSB first.

You could try directly swapping the order:

Alas, some tools won’t let you mix LSB- and MSB-first vectors in one expression.

A more general approach is to reverse the bits explicitly. All bits are swapped in parallel:

Updating individual bits is tedious, but a for loop can handle this for us:

Verilog for is NOT like a software loop: this for loop is unrolled into parallel bit swaps.

Big Endian, Little Endian

So far, we’ve been talking about ordering at the bit level, but it also occurs in the context of bytes. If you have a 32-bit word, do you store the least significant byte at the lowest address (little-endian) or the most significant byte at the lowest address (big-endian)?

RISC-V, x86, and ARM are little-endian, while Internet protocols (TCP/IP) and Motorola 68K are big-endian. There’s also the cursed middle-endian, but I won’t discuss that here.

I’m still writing this content.

What’s Next?

If you enjoyed this post, please sponsor me . Sponsors help me create more FPGA and RISC-V projects for everyone, and they get early access to blog posts and source code. 🙏

Part three covers Multiplication with DSPs or jump ahead to Fixed-Point Numbers .

You can also check out our other maths posts: division , square root , and sine & cosine .

We’re ignoring X and Z for the purpose of this introduction. See Numbers in Verilog .  ↩︎

• Stack Overflow for Teams Where developers & technologists share private knowledge with coworkers
• Advertising & Talent Reach devs & technologists worldwide about your product, service or employer brand
• OverflowAI GenAI features for Teams
• OverflowAPI Train & fine-tune LLMs
• Labs The future of collective knowledge sharing
• About the company Visit the blog

Collectives™ on Stack Overflow

Find centralized, trusted content and collaborate around the technologies you use most.

Q&A for work

Connect and share knowledge within a single location that is structured and easy to search.

Get early access and see previews of new features.

<= Assignment Operator in Verilog

What does the <= do in Verilog?

For example:

• 1 Please check, stackoverflow.com/questions/4653284/… –  Jithin Commented Mar 24, 2015 at 13:46

6 Answers 6

"<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators.

It is Recommended to use non-blocking assignment for sequential logic and blocking assignment for combinational logic, only then it infers correct hardware logic during synthesis.

Non-blocking statements in sequential block will infer flip flop in actual hardware.

Always remember do not mix blocking and non-blocking in any sequential or combinational block.

During scheduling process of simulator:

There are four regions and order of execution of commands as follows

Using of blocking assignment "=" for two variable at the same time slot causes race condition

eg: Verilog code with race condition,

In order to avoid race condition use non-blocking statement "<="

When this block is executed, there will be two events added to the non blocking assign update queue. Hence, it does the updation of BCD1 from BCD0 at the end of the time step.

Using Non-blocking "<=" assignment in continuous assignment statement is not allowed according to verilog LRM and will result in compilation error.

Only use NBA in procedural assignment statements,

This is called a 'non-blocking' assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables.

For example, in this code, when you're using a non-blocking assignment, its action won't be registered until the next clock cycle. This means that the order of the assignments is irrelevant and will produce the same result.

The other assignment operator, '=', is referred to as a blocking assignment. When '=' assignment is used, for the purposes of logic, the target variable is updated immediately.

The understand this more deeply, please look at this example (from Wikipedia):

In this example, flop1 <= flop2 and flop2 <= flop1 would swap the values of these two reg s. But if we used blocking assignment, = , this wouldn't happen and the behavior would be wrong.

Since people have already explained the blocking/non blocking situation, I'll just add this here to help with understanding. " <= " replaces the word "gets" as you read code

For example :

.... //Verilog code here

A<=B //read it as A gets B

When does A get B? In the given time slot, think of everything in hardware happening in time slots, like a specific sampled event, driven by clock. If the "<=" operator is used in a module with a clock that operates every 5ns, imagine A getting B at the end of that time slot, after every other "blocking" assignments have resolved and at the same time as other non blocking assignments.

I know its confusing, it gets better as you use and mess up bunch of designs and learn how it works that way.

"<=" is a non-blocking assignment operator in verilog."=" is a blocking assignment operator.

Consider the following code..

The values of a and b are being exchanged using two different always blocks.. Using "=" here caused a race-around condition. ie. both the variables a and b are being changes at the same time.. Using "<=" will avoid the race-around.

Hope i helped too..

<= is a non blocking assignment. The <= statements execute parallely. Think of a pipelined architecture, where we come across using such assignments.

A small exammple:

// initialise a, b, c with 1, 2 and 3 respectively. initial begin a <= 1 b <= 2 c <= 3 end

always@(clock.posedge) begin a <= b b <= c c <= a end

After the first posedge clock: a = 2, b = 3, c = 1

After the second posedge clock: a = 3, b = 1, c = 2

After third posedge clock: a = 1, b = 2, c = 3

As most told, it is a "Non Blocking <=" assignment widely used for Sequential logic design because it can emulate it best.

Here is why :

Mostly involving a delay(here posedge clock) it is something like it schedules the evaluation of the RHS to LHS after the mentioned delay and moves on to the next statement(emulating sequential) in flow unlike "Blocking = " which will actually delay the execution of the next statement in line with the mentioned delay (emulating combinational)

Your Answer

Reminder: Answers generated by artificial intelligence tools are not allowed on Stack Overflow. Learn more

Sign up or log in

Post as a guest.

Required, but never shown

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy .

Not the answer you're looking for? Browse other questions tagged verilog or ask your own question .

• The Overflow Blog
• Where does Postgres fit in a world of GenAI and vector databases?
• Featured on Meta
• We've made changes to our Terms of Service & Privacy Policy - July 2024
• Bringing clarity to status tag usage on meta sites
• What does a new user need in a homepage experience on Stack Overflow?
• Staging Ground Reviewer Motivation
• Feedback requested: How do you use tag hover descriptions for curating and do...

Hot Network Questions

• Derivative of max over a parameter
• Optimal Bath Fan Location
• Fill a grid with numbers so that each row/column calculation yields the same number
• How much missing data is too much (part 2)? statistical power, effective sample size
• What would be non-slang equivalent of "copium"?
• Can't see parts of a wall when viewed through a glass panel (shower cabin) from a top view angle
• What did the Ancient Greeks think the stars were?
• Trying to find an old book (fantasy or scifi?) in which the protagonist and their romantic partner live in opposite directions in time
• What issues are there with my perspective on truth?
• What is the significance of bringing the door to Nippur in the Epic of Gilgamesh?
• How can I draw water level in a cylinder like this?
• pgf plots-Shifting the tick label down while changing the decimal seperator to comma (,)
• Is every recursively axiomatizable and consistent theory interpretable in the true arithmetic (TA)?
• Why doesn't the immune system ever destroy the glucagon-producing alpha cells in the pancreas? Why only insulin-making beta cells?
• about flag changes in 16-bit calculations on the MC6800
• CPU is idle, but huge load, and NFS client stop responding
• Using "no" at the end of a statement instead of "isn't it"?
• A string view over a Java String
• Can a 2-sphere be squashed flat?
• Is there any video of an air-to-air missile shooting down an aircraft?
• What happens if all nine Supreme Justices recuse themselves?
• Purpose of burn permit?
• Generalization of a simple result in Linear Algebra
• Does the Greek used in 1 Peter 3:7 properly translate as “weaker” and in what way might that be applied?

An Introduction to Verilog Data Types and Arrays

In this post, we talk about the most commonly used data types in Verilog. This includes a discussion of data respresentation , net types , variables types , vectors types and arrays .

Although verilog is considered to be a loosely typed language, we must still declare a data type for every port or signal in our verilog design.

The type which we specify is used to define the characteristics of our data.

We can use types which interpret data purely as logical values, for example. We can also use types which interpret our data as if it were a numeric value.

When we assign data to a signal in verilog, the data is implicitly converted to the correct type in most cases. As a result, there is often no need necessary to explicitly perform type conversions in verilog.

• Get the Video Tutorial

Purchase the video tutorial using the Fourdotpay Wallet.

We'd really appreciate your feedback on these videos and the Fourdotday payment portal. For feedback on the videos, please contact us on [email protected] . For feedback on the Fourdotpay platform, please contact us on [email protected]

Payments for our videos are handled by a new company called Fourdotpay . Anyone who signs up with them during this introductory period will receive a  £5 welcome bonus .  This means you can try out one of our new videos absolutely free. See our FAQS page for details about how to take advantage of this offer.

• Respresenting Data in Verilog

When we write verilog, we often need to represent digital data values in our code. We can express this data as either a binary , hexadecimal or octal value.

Unlike in other programming languages, we also need to define the number of bits we have in our data representation.

This is because we are fundamentally describing hardware circuits when we use verilog. Therefore, we can create data busses which contain as many bits as we choose.

The code snippet below shows the general syntax for representing digital data in verilog.

We use the <bits> field to indicate the number of bits in the data that we are representing.

We use the <representation> field to indicate how our data is represented. This field can be set to b (for binary), h (for hex), o (for octal) or d (for decimal).

Finally, we use the <value> field to set the actual value of the data.

The code snippet below shows how we represent the decimal value of 8 using each of the different valid reprentations.

Basic Data Types in Verilog

Broadly speaking, the basic data types in verilog can be split into two main groups - net types and variable types .

We use these two different groups to model different elements of our digital circuits.

We use the net types to model connections in our digital circuits. They are unable to store values on their own and must be driven with data.

We primarily use the variable types to model registers or flip flops in our design. These types can store data, meaning that their behaviour is similar to variables in other programming languages such as C.

Regardless of the exact type we are using, there are four valid values we can assign to individual bits in our data. These four different values are shown in the table below.

We use the same syntax to declare a variable in verilog, regardless of the exact type. The code snippet below shows this general syntax.

We use the <type_name> field in the above example to declare the type of variable we have. We simply replace this field with the name of the type.

As an example, the verilog code below declares an integer type variable and assigns it a value of 100.

Net Types in Verilog

We use the net data types in verilog to describe the physical connections between different components in our design. As a result of this, net types on their own can not be used to store data values or drive data.

To better demonstrate when we would use a net type, consider the circuit diagram shown below.

In this circuit, we would use a net type to connect the output of the multiplexor to the input of the flip flop.

We normally use continuous assignment to drive data onto a wire type. To do this we must use the assign keyword, as shown in the code snippet below. We talk about continuous assignment in more detail in a later post.

We can not use net types in procedural code such as always blocks . The always block is discussed in more detail in a later blog post.

• Wire Type in Verilog

The most commonly used net type in verilog is the wire type which we discussed in the previous post.

We use the wire type in verilog to declare signals which are very basic point to point connections in our design. As the name suggests, they are roughly equivalent to an electrical wire in a traditional circuit.

The verilog code below shows how we use the wire type together with the assign keyword.

• wand & wor Types

Although the wire type is the most commonly used of the net data types, there are several other types of net which we can use in our verilog designs.

The wand and the wor net types are used to insert basic logic gates into our circuit. We use the wand to insert an and gate and the wor type to create an or gate.

When we use the wand and wor types, we must assign the signal more than once. We do this as each of the assignments represents one input to the underlying logic gate.

The verilog code below shows how we use the wand and wor types together with the assign keyword.

As we will see in a later post, we can easily use the wire type to model combinational logic in verilog . As a result of this, the use of the wor and wand types is not recommended.

• tri, triand & trior Types

In addition to the wire, wand and wor state, we can also use an equivalent tri, triand or trior type.

We use these types in the exact same way as the wire, wand and wor types. In fact, the functionality of these types is exactly the same. However, we can use them to more clearly show the intent of our design.

The code snippet below shows a basic example where the tri type is driven to high impedance .

However, as the wire type can also can take tristate values, we rarely use the tri type in practise. The same is also true with the trior and triand types, which can also easily be replicated using the wire type in our verilog designs.

• supply0 & supply1 Types

The final net types which we can use in our verilog designs are the supply0 and supply1 types.

We can use these types to tie our signal to a constant value of either binary 1 or 0. As this has the effect of creating a net which is tied to either ground or Vcc , we don't need to assign any data to this type.

The code snippet below shows how we use these types to create a signal which is tied either high or low.

However, we rarely need to tie a signal high or low in our design and when we do, it is simple to accomplish using a wire type. Therefore, the supply0 and supply1 types are rarely used in practise.

Variable Types in Verilog

Unlike net types, we use variable data types in verilog to store values. When we assign a value to a variable type it maintains this value until it is assigned again.

The variable types are generally more intuitive to understand than net types as they behave in a similar manner to variables in languages such as C .

To better demonstrate when we would use a variable type, consider the circuit diagram shown below.

In this circuit, we would use a variable type to model the flip flop output as it effectively stores a single bit of data.

We must use variable types within blocks of procedural code such as an always block , as shown in the code snippet below which models a D type flip flop .

• Reg Type in Verilog

The most commonly used variable type in verilog is the reg type. We can use this type whenever we need to store a value in our design.

We most commonly use the reg type to model the behaviour of flip flops.

However, the reg type can also be used to model combinational logic in verilog in some circumstances.

We discuss the use of the reg type for modelling both types of logic in more detail in the post on the verilog always block .

The verilog code snippet below shows how we use the reg type to model a basic flip flop.

Numeric Variable Types

The types which we have looked at so far are all used with single bits of data. However, we can also represent data numerically in our verilog designs.

In verilog, there are two commonly used numeric types - the integer type and the real type . Let's take a closer a look at both of these types.

• Verilog Integer Type

The most commonly used type for numerical data in verilog is the integer type. However, we normally use this for internal signals in a module rather than for ports. 

By default, the integer is a 32 bit 2s complement number which we can use to represent any whole number in our verilog design.

When we use an integer type, we assign numerical rather than binary values to the variable.

As we can also assign numeric values to the reg type, we typically use integers for constants or loop variables in verilog.

Our synthesis tools will automatically trim any unused bits in our integer type. For example, if we declare an integer constant with a value of 255 then our synthesis tool will trim this down to 8 bits.

The code snippet below shows how we declare and assign an integer type in verilog.

• Verilog Real Type

In addition to the integer type, we can also use the real type in verilog. We use this type to store non-integer numbers, i.e. numbers which also have a decimal part.

The real type is typically implemented as a 64 bit floating point number in verilog. As a result of this, it can't be directly synthesized and we typically only use the real type in our verilog testbenches .

We can use either decimal or scientific notation to assign values to the real type.

The code snippet below shows how we declare a real type and assign data to it.

• Vector Types in Verilog

With the exception of the numerical types, all of the types which we have looked at so far consist of a single bit.

However, we often use data busses to transfer data within a digital circuit.

In verilog, we can use vector types to create data buses. This allows us to declare a signal which has more than one bit.

The code snippet below shows the general syntax which we use to declare a vector type in verilog.

When we define the size of the vector we must specify the most significant and least significant bits (MSB and LSB). Therefore, the <size> field takes the form [MSB:LSB].

For example, to declare a 4 bit little endian type vector we would use the construct [3:0].

As we talked about earlier in this post, we can represent data using binary, hex, octal or decimal formats. When we assign data to a vector we can use any of these representations.

The verilog code below shows how we would declare a 4 bit wide reg type. We also see how we can use the different data representations to assign the value of 1010b to the variable.

• Signed and Unsigned Data in Verilog

Prior to the release of the verilog 2001 standard all variable and net types could only be used to store unsigned data types.

Similarly, the integer type was always interpreted as a signed value.

However, the signed and unsigned keywords were introduced as a part of the verilog 2001 standard. This allows us to change the way our variable interprets data.

When we declare a type as signed in verilog, it is interpreted as a 2's complement number. This means that we can assign negative numbers to these signals.

By default, the integer type is signed whilst both the reg and wire types are unsigned. We only need to use these keywords if we wish to modify this default behaviour.

The verilog code below shows how we can declare signed and unsigned data using the reg, wire and integer types. In this case, all of the variables which we declare are 32-bits wide.

Arrays in Verilog

We can also create and use array types in verilog. These are particularly useful in the modelling of memories.

In order to declare an array in verilog, we simply add an extra field after the variable name which declares how many elements there are in our array.

This declaration takes the same format as the vector size field which we talked about previously.

The code snippet below shows the general syntax which we use to declare an array type in verilog. We use the <elements> field to declare the size of our array.

As an example, let's say we want to create an array of 3 bit reg types. We want to have a total of 8 elements in the array. The verilog code below shows how we would create this array.

We can access individual elements in the array type using square brackets. For example, the verilog code below shows how we would assign the value of 5h to the final element in our example array.

We can also simulate this example on EDA playground .

• Multi Dimensional Arrays

In the verilog 1995 standard , it is only possible for us to create one dimensional arrays such as those we used in the previous section.

However, we can also create arrays which have more than one dimension when we use the verilog 2001 standard.

To do this, we simply add another field which defines the number of elements we need.

The code snippet below shows the general syntax we would use to create a 2D array in verilog.

As an example, let's consider the case where we want to modify the size of the array from our previous example.

We now want to create a variable which can store 2 elements both of which have 8 4 bit reg type elements.

To do this, we simply add an extra field to the end of our declaration. The code snippet below shows how we would do this.

We also use the same method to assign a multidimensional array as we would for a 1D array. However, we now use a pair of square brackets to define the element in both dimensions of the array.

As an example, suppose we want to assign the value of 0xa to the the last element in both dimensions. The verilog code below shows how we would assign data to this element in our array.

Which types of data can we represent in our verilog design?

Binary, hexidecimal, octal and decimal. We can also represent decimal numbers but this is not synthesizable.

What are the two main data types in verilog? What is the difference between them?

Net types are used to model connections in our design and can’t store values. Variable types can store data values and behave like variables in other programming languages.

Which type do we most commonly use to model point to point connections in verilog?

The wire type

Which type do we most commonly use to model the behaviour of storage elements like flip flops?

The reg type.

Name the two different types of numeric types. What are the differences between them?

The integer type represents whole numerical values. The real type can be used to represent decimal values as well.

Write the code to declare an 8 bit wire type and assign it the value of AAh.

Declare an array of 16 bit reg types. The array should have a total of 4 elements. Assign the value of FFFFh to the first element in the array and AAAAh to the fourth element in the array.

2 comments on “An Introduction to Verilog Data Types and Arrays”

reg[16:0] example [3:0]; Should be reg [15:0] Not a serious one but it's worth correcting for the sake of neatness..:)

Thanks for pointing out the mistake, it has been corrected now.

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Save my name, email, and website in this browser for the next time I comment.

Table of Contents

Sign up free for exclusive content.

Don't Miss Out

We are about to launch exclusive video content. Sign up to hear about it first.

Reference Designer

• Tutorials Home

Verilog Basic Tutorial

• Verilog Introduction
• Installing Verilog and Hello World
• Simple comparator Example
• Code Verification
• Simulating with verilog
• Verilog Language and Syntax
• Verilog Syntax Contd..
• Verilog Syntax - Vector Data
• Verilog $monitor
• Verilog Gate Level Modeling
• Verilog UDP
• Verilog Bitwise Operator
• Viewing Waveforms
• Full Adder Example
• Multiplexer Example
• Always Block for Combinational ckt
• if statement for Combinational ckt
• Case statement for Combinational ckt
• Hex to 7 Segment Display
• casez and casex
• full case and parallel case
• Verilog for loop
• Verilog localparam and parameter

Sequential Ckt Tutorial

• Sequential Circuits
• Serial Shift Register
• Binary Counters
• Ring Counter

Misc Verilog Topics

• Setting Path Variable
• Verilog Tutorial Videos
• Verilog Interview questions #1
• Verilog Interview questions #2
• Verilog Interview questions #3
• Verilog Books
• Synchronous and Asynchronous Reset
• Left and Right shift >
• Negative Numbers
• Blocking Vs Non Blocking
• wand and wor
• delay in verilog
• $dumpfile and $dumpvars
• Useful Resources
• Verilog Examples

Verilog Quizs

• Verilog Quiz # 1
• Verilog Quiz # 2
• Verilog Quiz # 3
• Verilog Quiz # 4
• Verilog Quiz # 5
• Verilog Quiz # 6
• Verilog Quiz # 7
• Verilog Quiz # 8
• Verilog Quiz # 9

Other Tutorials

• Verilog Simulation with Xilinx ISE
• VHDL Tutorial

Verilog Language Continued

Copyright © 2009 Reference Designer

Tutorials | Products | Services | Contact Us

Vector assignment in system verilog

I defined a signal as

what is the difference between the following assignments if mem[addr] is a 16 bit vector?

The second assignment is illegal. When assigning you can only specify array dimensions, packed or unpacked, at the right side of array name. If you ask about difference between

logic [15:0] data logic data [15:0]

it is that dimensions specified before array name are “packed” dimensions which means that elements occupying these indexes are reliably positioned next to each other in memory. The dimensions specified after the array name are “unpacked” dimensions, which means those elements could be arranged in memory in a distributed way, as deemed optimal by the SV engine, not necessarily next to each other.

• Verilog Vectors

03 Aug 2021

In Verilog we have seen that we have 1-bit data types. But in hardware, many ports can have more than one bit has an input. Also, it can have registers which is nothing but a group of flip flops. Thus, Verilog provides us a way to use both single bit variables and multiple bits variable.

Scalar variables

Any reg or wire declaration, that has only one bit is known as scalar variables .

Vector variables

Any reg or wire declaration that has more than one bit is known as vector variables . The range is specified using [msb:lsb] or [lsb:msb] brackets just after writing the data type.

Vector Slicing

Any subpart of the vectors can be selected, and this is known as vector slicing . After declaring a vector, subpart can be selected using the [] brackets and providing the range in between. Vector slicing should be in the same order as it is declared. It means that the if during declaration msb is written first then, during slicing should be done from higher bits to lower bits and vice-versa.

Syntax for vector slicing: [<higer-bit>:<lower_bit>] or [<lower_bit>:<higer-bit>]

A disadvantage of this method is that we can't have a variable as a slicing parameter. Slicing parameter should always be constant. So, Verilog provides a one more way to slice vectors, in which we can use variables as parameter. Verilog provides +: and -: operators for slicing.

Syntax for using this slicing operator: [<starting_bit>+:<width>] [<starting_bit>-:<width>]

• Introduction to Verilog
• Verilog Event Semantics
• Basics of Verilog
• Verilog Syntax
• Data Types in Verilog
• Verilog Arrays
• Verilog Modules
• Verilog Ports
• Verilog Operators
• Verilog Procedural Blocks
• Verilog Assignments
• Different types of loops in Verilog
• Conditional Statements in Verilog
• Verilog functions and tasks
• Compiler Directives in Verilog
• Verilog System Functions
• Delays in Verilog

Verilog assign statement

Hardware schematic.

Signals of type wire or a similar wire like data type requires the continuous assignment of a value. For example, consider an electrical wire used to connect pieces on a breadboard. As long as the +5V battery is applied to one end of the wire, the component connected to the other end of the wire will get the required voltage.

In Verilog, this concept is realized by the assign statement where any wire or other similar wire like data-types can be driven continuously with a value. The value can either be a constant or an expression comprising of a group of signals.

Assign Syntax

The assignment syntax starts with the keyword assign followed by the signal name which can be either a single signal or a concatenation of different signal nets. The drive strength and delay are optional and are mostly used for dataflow modeling than synthesizing into real hardware. The expression or signal on the right hand side is evaluated and assigned to the net or expression of nets on the left hand side.

Delay values are useful for specifying delays for gates and are used to model timing behavior in real hardware because the value dictates when the net should be assigned with the evaluated value.

• LHS should always be a scalar or vector net or a concatenation of scalar or vector nets and never a scalar or vector register.
• RHS can contain scalar or vector registers and function calls.
• Whenever any operand on the RHS changes in value, LHS will be updated with the new value.
• assign statements are also called continuous assignments and are always active

In the following example, a net called out is driven continuously by an expression of signals. i1 and i2 with the logical AND & form the expression.

If the wires are instead converted into ports and synthesized, we will get an RTL schematic like the one shown below after synthesis.

Continuous assignment statement can be used to represent combinational gates in Verilog.

The module shown below takes two inputs and uses an assign statement to drive the output z using part-select and multiple bit concatenations. Treat each case as the only code in the module, else many assign statements on the same signal will definitely make the output become X.

Assign reg variables

It is illegal to drive or assign reg type variables with an assign statement. This is because a reg variable is capable of storing data and does not require to be driven continuously. reg signals can only be driven in procedural blocks like initial and always .

Implicit Continuous Assignment

When an assign statement is used to assign the given net with some value, it is called explicit assignment. Verilog also allows an assignment to be done when the net is declared and is called implicit assignment.

Combinational Logic Design

Consider the following digital circuit made from combinational gates and the corresponding Verilog code.

Combinational logic requires the inputs to be continuously driven to maintain the output unlike sequential elements like flip flops where the value is captured and stored at the edge of a clock. So an assign statement fits the purpose the well because the output o is updated whenever any of the inputs on the right hand side change.

After design elaboration and synthesis, we do get to see a combinational circuit that would behave the same way as modeled by the assign statement.

See that the signal o becomes 1 whenever the combinational expression on the RHS becomes true. Similarly o becomes 0 when RHS is false. Output o is X from 0ns to 10ns because inputs are X during the same time.

Click here for a slideshow with simulation example !

• Search forums

Follow along with the video below to see how to install our site as a web app on your home screen.

Note: This feature may not be available in some browsers.

Welcome to EDAboard.com

Welcome to our site edaboard.com is an international electronics discussion forum focused on eda software, circuits, schematics, books, theory, papers, asic, pld, 8051, dsp, network, rf, analog design, pcb, service manuals... and a whole lot more to participate you need to register. registration is free. click here to register now..

• Analog Design
• Analog Circuit Design

Vector Assignment @ Verilog-A

• Thread starter pru1977
• Start date Jan 20, 2012
• Jan 20, 2012

Newbie level 2

Hello together, just a quick, basic question regarding Verilog-A. What is the correct syntax for an assignment to a integer vector? What I want to do is the following: integer a[`BITS-1:0]; // BITS = 3 a <= 3'b111; // this assignment is done in the 'initial_step' section So, I want to set all bits of the vector a to a certain bit combination (in this case 111). I couldn't find the correct syntax for it in the Verilog-A reference manuals. Thanks for your help  

Similar threads

• Started by vug
• Jul 9, 2024
• Started by LiaoJJ
• Apr 28, 2024
• Started by mssong
• Feb 6, 2024
• Started by livecf
• Jun 16, 2023
• Started by wien
• Jul 10, 2024
• Replies: 17

Part and Inventory Search

Welcome to edaboard.com.

• This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register. By continuing to use this site, you are consenting to our use of cookies. Accept Learn more…