vhdl assignment types

Data Types in VHDL

In this article, we shall discuss data types in VHDL. After reading this article, you’ll be able to answer the following questions.

What are data types?

In VHDL, we define datatypes while initializing signals, variables, constants, and generics.

Also, VHDL allows users to define their own data types according to their needs, and those are called user-defined data types.

User-defined data types can be defined in a separate file and shared as a library. You can define a bunch of custom data types and put them in a library and use that whenever you want. Sort of like your personal toolkit!

Due to its usefulness, it is the most popular and widely used library in VHDL. It has useful datatypes like std_logic and std_ulogic which helps us to make simulation much more practical. And to make our VHDL programming easy, we use IEEE’s library and its functions quite often.

Significance of datatypes

Similarly, we store data values in variables of a suitable type. And the same analogy continues for other data objects like signals, constants, etc.

Consider a ‘signal Q’ whose datatype we don’t know yet. It is initialized with a value ‘0’. If we wish to change its value to ‘1’ later on. How we’ll do it?

As a programmer, you have the freedom to use a data type, but you should also utilize your wisdom to choose a suitable one.

Data types in the standard library

There are many data types defined in the standard library of VHDL. To make them easy to understand, we categorize them into the following four types:

Enumerated type

Boolean data type.

A Boolean type data object can have a single value. Either ‘FALSE’ or ‘TRUE.’ That’s it. The logical operations that can be performed on Boolean variables are “and, or, not, nand, nor, xor.”

Bit data type

A Bit type of data object can either have ‘0’ or ‘1’. The logical operations that can be performed on Bit variables are the same as of Boolean, i.e. “and, or, not, nand, nor, xor.”

Initializing a Bit type variable and a signal with an initial value:

Character data type

A character type data object can hold any one character or special character at a time or can hold sum defined literal like NUL, SOX, STX, etc.

All possible enumeration for a character data type

Severity levels.

The severity level data type can have the values ‘NOTE’, ‘WARNING,’ ‘ERROR,’ ‘FAILURE.’ Severity levels are used in assertion statements, which will be discussed in detail in an upcoming article, but, in short, they behave as logs (think of them like personal paper flags) while simulation to indicate if any error occurs and what is its severity.

So default value for data objects of datatype bit is ‘0’. And the same goes for all data types as mentioned in the table below

Numeric type

Integer data type.

Now, what are subtypes you ask, in short, a subtype is a datatype which has constrained values of its base type. Sound confusing?

Real data type

It can hold floating-point numbers ranging from -1.0E38 to +1.0E38. These are very helpful for precise calculation. For example, if we need to use the value of pi (π) for some calculations, then we can’t use an integer to store its value (3.14159). An integer can only store 3, which decreases preciseness of calculations. But a real can store floating digits of up to 6 decimal places.

Array data types

Bit vector -A bit_vector is simply an array of grouped bits, they are useful while defining multiple pin inputs. Consider an example. You are creating a 4-bit adder so you’ll need 4-bit inputs, rather than defining them individually you can use:

Miscellaneous

There are two data types in the standard library, i.e., ‘TIME.’ This is used to store values that can be further utilized for timing operation, like creating specific delays. Some units of time are also defined in the standard library, as shown below:

Data types from non-standard libraries

We use it to represent much more practical details of digital signals in circuits and wires.

'H' : This signal is also weak but it should probably go to 1

std_logic – This datatype has the same enumeration as of std_ulogic . However, the difference is that std_logic is resolved and we don’t need extra resolution function.

'L' : This signal is also weak that it should probably go to 0

Initializing a Std_logic type variable and a signal with an initial value:

The statement above assigns ‘0’ to input(0), ‘1’ to input(1), and so on.

In the code above, we have created a record named ‘MODULE,’ and it has 4 data objects inside it. Now MODULE is a datatype in itself.

The above line of code assigns “50” to SIZE, “20 ns” to DELAY, “3” to NO_OF_INPUTS, and “2” to NO_OF_OUTPUTS.

Bit and bit_vector

We will be talking only about the program of 2×1 multiplexer , so if you are interested in working on it, then we have a separate article here .

In the above code, three ports are initialized, two inputs, and one output. For data input in 2×1 mux, we need 2-bit input we may use two different bits as

This creates 2-bit input as input(0) and input(1) and assigning values to them is way more comfortable as

As always, if you have any queries, we would love to address them. Just drop in a comment in the comments section below.

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Understanding VHDL

Table of contents, 1. vhdl hardware description language, 2. design styles, 3. vhdl abstraction levels, 4. structure of vhdl modules, 5. vhdl data types, 6. vhdl variables, signals, constants, 7. vhdl operators, basics, structure, data types and operators.

Hardware description languages (HDL) are used to design digital and electronic systems. Today, the languages most widely employed are VHDL and Verilog. These description languages allow the user to write a program that describes the behavior of the circuit. This program can be used to simulate the operation of the circuit. And its implementation can be synthesized in a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or an Application Specific Integrated Circuit (ASIC).

VHDL stands for Very High-Speed Integrated Circuit Hardware Description Language and is what its name implies: a hardware description language. It is based on the ADA software programming language; the syntax is similar, but the way it behaves is different. VHDL models, describes, and simulates digital or electronic circuits and systems. Although VHDL and sequential programming languages (e.g., C / C++) look similar, VHDL handles sequential and concurrent executions. It also incorporates timing specifications (gate delays). Using an Electronic Design Automation (EDA) tool, a high-level VHDL behavioral model can be translated into a gate level netlist which describes the circuit in terms of gates and connections between them. The netlist is placed and routed to generate a layout. This layout created by the EDA tools is sometimes used to produce the electronic systems.

VHDL has many advantages:

• it supports design methodologies like top-down and bottom-up approaches,
• it provides a flexible design language,
• it allows a detailed implementation and a better design management,
• it has support for multi-level abstraction,
• it strongly supports code reusability and sharing.

Hardware description languages use two design methods: bottom-up or top-down. Nowadays, a hardware design uses both methodologies to implement a structure. In a top-down design approach, the designer adds details as the design progresses. First, he defines the top-level block and moves down to the smallest elements. Like a tree, the design starts from the roots (top-level block) and adds branches with the sub-blocks necessary to build the top-level.

The bottom-up methodology uses the smallest details to build the blocks, after which these blocks are used to create larger blocks. Thus, the top-level is built using blocks that are getting more and more abstract as the code is added. Top-down and bottom-up workflows are frequently combined. The top-level block's parameters are determined by the design architects. Logic developers divide the functionality into blocks and sub-blocks to determine how the design should be organized. Circuit designers are creating optimized circuits leaf-level cells. These leaf cells are then used to create higher-level cells. The logic-level designers start to design from the top and move down until all modules are defined in terms of leaf cells. The flow meets at this intermediate point, where the switch-level circuit designers have created a library of leaf cells using switches.

When discussing the various levels of abstraction in VHDL, it is all about the different styles of description. Thus, there are 3 major levels: behavioral, structural, and dataflow.

At this level, the model is represented by a functional description and is employed at the beginning of a design to be able to run a simulation. It is used mostly in test-bench design, because in the test-bench phase it is not so relevant if the hardware is achievable. Compared to other levels, behavioral is considered the highest abstraction level. At this level, a system is described in an algorithmic mode and does not imply a gate-level implementation. The behavioral level comprises one or more process statements, and each contains one or more sequential statements. In a simulator, all the statements are executed sequentially, similar to a conventional programming language.

Behavioral modeling uses sequential statements to describe a behavior of an entity. This makes it very similar to high-level programming languages, like C, C++, or JAVA. “Process” statements and various sequential statements are used to write this behavioral model. In VHDL, the descriptions of all processes are executed concurrently, but the statements included in the process description are executed sequentially.

A process label is just a name for a particular process. Assigning labels is especially useful while writing large pieces of code. They are not required, and their absence will not create any errors. A so called “sensitivity list” identifies all the signals by their name that the process is sensitive to. This list is optional, but without it, a process will run forever, unless a wait statement is included at the end of a process.

Example: 2-to-1 Multiplexer in behavioral modeling style.

The mode of operation of the multiplexer is declared in the architectural body, where the multiplexer sends the input signal from the user-specified address to its output. For the process to work properly, it must monitor the input ports. For this reason, the sensitivity list contains all three ports. Using IF … ELSIF statements, the multiplexer functionality can be created, and all these statements are running sequentially.

VHDL structural modeling is similar to doing a schematic design, but it uses text instead of block diagrams elements. This type of modeling has several advantages when it comes to large and complicated projects. Using a structural style, a big project can be split into two or more simple designs to make it easier to handle the complexity of the project. This allows to pack low-level functionality into modules. This way, already implemented modules can be reused without having to rewrite the design from scratch. In order to use this level of abstraction, one or more components need to be instantiated inside a design. For this, one or more architecture declarations need to be created. An architecture contains two parts, the declarative part and the statement section. In the declarative part, a component is declared with the ports that it uses. The statement section describes the way the ports interact with each other.

Example: 2 gates, AND & OR, connected in series

In this code, the output of an AND2 gate is linked to one of the inputs of an OR2 gate and compared with another signal.

VHDL dataflow modeling follows the way the data flows through the design, from input to output. This abstraction level specifies the functionality of a design without specifying its structure. This involves the description at a gate level of the appropriate logic gates (AND, OR, XOR, etc.). The dataflow uses one or more signal assignment statements. They can be used sequentially or in parallel. For this level, sequential designs are used, the output depends on the input and the previous states. Therefore, “memories” need to be used for the system designs.

For this abstraction level, several ways to implement a design are possible:

• concurrent signal assignments,
• conditional signal assignments,
• selected signal assignments.

For example, a multiplexer is a combinational circuit that selects, based on selection lines, one out of several inputs and sends it directly to the output. The table illustrates the truth table for a 4×1 multiplexer. Here, the Y column is the output with the selected port.

Example: Multiplexer using conditional signal assignment

Example: Multiplexer using selected signal assignment

VHDL Libraries and Packages

Libraries are a collection of packages that define the operators and operations in the logic utilized to describe a digital system. The IEEE library is commonly used; it defines a binary representation consisting of values of 0 and 1, and a standard logic representation (std_logic) with nine distinct logic values, of which the most important are: 0, 1, X (unknown) and Z (high impedance). To include a library in VHDL, the reserved word library is used in an instruction of this form:

Packages are a collection of elements, like data types, subprograms, constants, or operators, within a library. The reserved word for the inclusion of a package from a library is use, the instruction is written as:

For the IEEE library, to use the logic primitive’s description, it is required to include the package IEEE.std_logic_1164. For this, write the following code sequence:

VHDL Modules

The declaration for interface-signal uses this form:

• mode – indicates the direction of the signal: in, out, inout, buffer.
• in – carries information into the module, can be read but not updated in the module
• out – carries information out of the module, can be updated but not be read inside a module
• inout – can be read and updated, this mode is bidirectional
• buffer – carries information out of a module, and can be both updated and read from the module
• type – indicates the signal type: bit, boolean, std_logic, integer, real, character, time
• optional : a default value

For example, the next lines of code are the declaration for the entity of an and-gate with two inputs and one output:

The architecture descriptor – architecture – describes the function of the digital circuit. In this part of a module, one or more abstraction level presented above are combined to create an architecture. The code can set out how the circuit behaves using functional blocks and the connection between them, or a mathematical description of the logical functions (truth table, transition diagram, algorithm). The declaration of an architecture uses this form:

In the declaration, the signals and constants are assigned if they are needed. To describe logical primitives, the body of VHDL module architectures consists of:

• assignment operators:
• fundamental logic operators (not, and, or, nand, nor, xor, xnor)

Example: The and-gate architecture with two inputs described with fundamental logic and is:

VHDL Module Instantiation

Module instantiation is used to connect circuit elements. At the top level, the connection is made between modules, and the EDA tool creates the netlist for all the components and connections that are used. A VHDL design description written exclusively with component instantiation is known as “Structural VHDL”. This method is very similar to the schematic entry; in this case, instead of using graphic elements, it is implemented as text. One or more components can be declared in the architecture body. To instantiate a component inside a design, the following two steps are needed:

• declare the components in the declarative part of the architecture, and
• instantiate the component in the architecture statement section.

The declaration section of the architecture is included between the keyword “is” and “begin”:

For example, to instantiate the and-gate with two outputs modules in another architectural model, the simplest way is to copy the entity of and2 and paste it to the architectural body. After that, change the “entity” to “component”.

• Predefined data types:

* users defined data, for example, enumeration:

VHDL is a strongly typed language, so different data types cannot be combined in the same instruction.

Vector Types

When designing with a hardware description language, data buses are often used. Data buses comprise multiple bit buses. The data types presented above allow single bits to be modeled in a design. A vector consists of one or more bits that are modeled similarly to one of the predefined data. The most basic and encountered types of vectors in VHDL are made up of several bit or std_logic types. The code below is an example of how to declare a vector type signal in VHDL.

The [ range ] field is used to determine the number of bits in the vector and the location of the most significant and least significant bits. The key word used to describe the range value in VHDL are: downto and to. The next lines present a declaration of an 8-bit vector using the keywords:

Conversion Type

When writing VHDL code, it is often necessary to do a data conversion. Two general methods to convert between data types are available. The first method is to cast the signal to the correct type. In this method, it is converted between the signed, unsigned and std_logic_vector.

The code below is an example demonstrating the syntax to cast signals or data.

The second way employs functions. This method is used to convert between the signed or unsigned types and the integer type. To use a suitable conversion function, it is needed to include either the numeric_std or the std_logicarith packages. These packages are available in the IEEE library.

Assigning Data Values

When assigning data to a vector type, VHDL uses quotation marks (“) instead of apostrophes. Also, it can specify to use a hexadecimal notation by adding an ‘x’ to the start of the data. This works if the number of bits is a factor of four. Using octal values can be done by adding an ‘o’ to the start of the data. This works only with VHDL-2008. The code below gives some examples of how to assign data to vector types in VHDL.

Because VHDL is similar to other programming languages, it allows variables. These are declared in the architecture declaration area.

• variable – receives a value that can be updated during running simulations
• signal – time-dependent size that maps to ports
• constant – receives a value that cannot be modfied during simulation

Example: In this example, several variables of each of the above types are declared and used in a small code combination:

VHDL has a set of operators that can be used in creating designs. Predefined operators:

Example 1: After declaring the variables, f is assigned the value between a and b using a binary operator. The binary operator “and” can be replaced with another binary operator according to the designer's need. This operation is performed after the delay; for this task, the timing operator “after” is used.

Example 2: Uses the timing operator “wait” to implement a breakpoint and wait for an event specified to happen:

Example 3: Uses different shift operators to make changes at a bit level.

Example 4: The combined use of several operators:

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VHDL Record, Array and Custom Types

In this post, we talk about the methods we can use to create our own custom data types in VHDL , including arrays and record types.

In the previous post we talked about the basic predefined types in VHDL . Whilst these are adequate for the majority of cases there are occasions when we require a custom data type in our code.

In VHDL, the most commonly used custom types are the enumerated types. These provide us with a technique for creating an entirely new type with custom values.

However, we can also create sub types which allow us to modify the range of values in one of the predefined VHDL types. In fact, the inbuilt VHDL positive and natural types are both example of subtypes which limit the range of values the integer can accept.

In addition to this, we can also use array and record types in our VHDL designs. This can provide us with a more structured design which is easier to maintain.

In the rest of this post we will at the methods we use to create all of these custom types in our VHDL code.

Creating Custom Types

When we write VHDL code, there are instances when the predefined types we wish to create a new type. One of the most common use cases is creating an enumerated type which we us to implement finite state machines (FSM) .

Actually there are two ways in which we can create a custom type in VHDL. We can either create an entirely new type or we can create a subtype .

Let's take a look at both of these methods.

• Type Declaration in VHDL

It is possible for us to create an entirely new type to use in our VHDL design. To do this, we must create a new name for our type and then associate some valid values with it.

The code snippet below shows the general syntax we use to create an new type.

The list of values is a comma separated list of all the values of our type can have.

When declaring a new type in VHDL we typically create an enumerated type. This means our list of values are just strings, or words, which we can assign to any instances of the type.

As an example, let's create a new type which we use to store the state of a small FSM. This is one of the most common reasons for creating a new type in VHDL.

For this example, our FSM will have just four states - idle, starting, runnning and stopping.

The code snippet below shows how we would create this type in VHDL. We can see that this is an enumerated type, meaning the list of values are simple strings.

Once we have created this type, we can create an instance of it in our code. We can then assign any value to it which we have listed in the declaration.

The code snippet below shows how we would create a signal using our custom type and assign it to the idle state.

• Subtype in VHDL

The second method we can use to create a custom type modifies one of the existing types. To do this, we use the subtype VHDL keyword and restrict the range of valid values which the new type can take.

The code snippet below shows the general syntax we use when creating a sub type.

One of the most common uses for the sub type keyword in VHDL is to restrict the number of bits in an integer type.

As an example, we may want to declare an integer which only uses 8 bits. In this case we can declare a new subtype and limit the maximum value to 255. The code snippet below shows how we would do this.

After we have created a new subtype, we can create instances of it to use in our VHDL design. We can then assign it any of the values we specified in the declaration.

The code snippet below shows how we would create a signal using our new type.

• Creating Array Types in VHDL

We can create our own array types in VHDL. To do this, we include the array keyword in the type definition. We must also declare the number of elements in the array.

The code snippet below shows the general syntax we use to declare an array type in VHDL.

The <type> field in the above construct can accept any VHDL type, including custom types we have declared. This means we can also build multidimensional arrays by using array types in this field.

The <range> field in the above example can be built using the downto and to VHDL keywords which we have seen before.

However, we can also use two special constructs which effectively create an unconstrained array type. This allows us to define the size of the array whenever we declare a port or signal which uses it.

To do this, we use the natural <range > or positive <range> keywords in the <range> field. The difference between the two is that the natural <range> option allows for zero based array numbering whereas positive <range> doesn't.

The VHDL code below shows the general syntax we use to create unconstrained array types.

Once we have declared a custom array type it can be used in an entity port, as a signal or a as a variable.

• An Example Array Type

To demonstrate how we declare a custom array type, lets consider a basic example. For this example we will create an array of 8 bit std_logic_vector types.

In addition, we will not constrain the array when we declare it. Instead, we will use the natural <range> construct so that we can change the size as we declare signals.

The code snippet below shows how we declare and use our custom array type.

Record Type in VHDL

We can create more complex data types in VHDL using a record. Records can contain any number of different signals which we want to group together. These signals don't need to be of the same type.

We can think of records as being roughly equivalent to structs in C.

We often use records to simplify the port list in a VHDL entity . If we have a number of common signals, we can group them together in a record. We can then use this record as part of the entity which reduces the number of ports we require.

Using record types in an entity can also improve the maintainability of our code. The main reason for this is that we only need to manage the contents of a record in the place it is declared. Therefore, we can change connections in our ports just by modifying the record type. If our design features multiple modules which use the same record, this can reduce the effort require to modify connections between entities.

• Declaring and Using a Record in VHDL

When we want to use a record in VHDL we must declare it as a type. We most commonly declare records inside a VHDL package . This allows us to use the record type in multiple different design files.

The code snippet below shows the general syntax we use to declare a record type in VHDL.

After we have declared a record type, we can use it in the exact same manner as any other port or signal in our VHDL design. We can assign data to individual elements in the record or to the entire array.

The code snippet below shows the two methods we can use to assign data to the record.

It is also possible for us to include records as elements in an array.

• An Example Record Type

Lets consider a basic example to better demonstrate how a record type works in VHDL. For this example, we will write a record which contains all the signals required in a UART interface.

The UART interface consists of 4 different signals. Each of these signals are a single bit which means we can use a std_logic type to model them.

The code snippet below shows how we would declare this record type.

After we have created the record, we can then use it in the type field for any port or signal in our VHDL design.

The code snippet below shows hows we would declare a signal which uses our UART record type.

Finally, we will obviously also want to drive data onto our record signal. The VHDL code snippet below gives some examples of how we can assign data to the record.

Write some VHDL code which creates an enumerated type for an FSM. The FSM has 4 states – idle, running, stopped and error

Create an integer subtype which can have a value between 5 and 200.

Write some VHDL code which declares an array of 8 32-bit std_logic_vectors

Write a record type which consists of an 8 bit unsigned type, a std_logic type and an unconstrained integer.

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Review of VHDL Signed/Unsigned Data Types

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This article will review the “signed”/“unsigned” data types.

In recent articles we’ve looked at some important VHDL data types: std_logic , std_logic_vector , bit, boolean , and integer . This article will review the “signed”/“unsigned” data types, which can be used when dealing with whole numbers.

Signed/Unsigned Data Types

As shown in Figure 1, the signed/unsigned data types are defined in the “numeric_std” package. This package is included in the “ieee” library.

Figure 1. The “signed” and “unsigned” data types are defined in the numeric_std package.

To use “signed” and “unsigned” data types, we need to include the following lines in our code:

Note that the “std_logic_1164” package is required because the “numeric_std” package uses the “std_logic” data type. In fact, similar to the “std_logic_vector” data type, the “signed” and “unsigned” data types are a vector of elements of type “std_logic”. However, unlike the “std_logic_vector” type, the “signed” and “unsigned” types have a numeric interpretation. Consider the following code:

The above code defines three signals, slv1 , sig1 , usig1 , of type “std_logic_vector”, “signed”, and “unsigned”, respectively. Then, it assigns “101” to these three signals. As discussed in a previous article , we cannot assume a weight for the different bit positions of a “std_logic_vector”. Hence, slv1 only represents a sequence of ones and zeros, with no other interpretation. However, usig1 and sig1 have numeric interpretations: usig1 is interpreted as the unsigned binary representation of 5, and sig1 is interpreted as -3. Note that VHDL uses the two’s complement technique to represent negative values.

Since the types “signed” and “unsigned” use “std_logic” as their base type, we can assign an element of type “signed”/“unsigned” to a “std_logic” object. For example, if s1 is declared as a “std_logic” signal, the following assignment is valid:

While the “std_logic_vector”, “signed”, and “unsigned” data types are closely related, we need to be careful when assigning these data types to each other. For example, the following assignments are illegal:

For these assignments, we have to first perform type casting and then the assignment operation. Type casting is a way to convert an object from one data type to another data type. Type casting and type conversion will be discussed in a future article.

Arithmetic Operations with “Signed”/“Unsigned” Types

The package “numeric_std” defines arithmetic operations for the “signed” and “unsigned” data types. The following code is an example where two four-bit unsigned objects are added together.

Figure 2 shows a simulation of this code. Note that this figure represents the decimal equivalent of the values to simplify verification of the simulation result.

There are two points that need further attention:

First, the numeric operations are generally defined such that the data path width does not change. For example, in the above code two four-bit numbers are added together and the result is assigned to another four-bit object. Consequently, we have to account for the possibility of overflow (because two four-bit numbers can produce a five-bit sum). If we resize the inputs and represent them with one extra bit, then overflow will not occur. This will be further discussed in the upcoming examples.

Second, the above example shows that we can add two “unsigned” values together, but what other options are there? For example, does VHDL allow us to mix the types and add an “unsigned” value to a “signed” one? Does it allow us to add a “signed” or “unsigned” value to the value represented by a “std_logic” signal? It turns out that the left and right operands of the addition (and subtraction) operator can be as listed in the following table. The table also shows the type of the result.

Each row of this table shows one possible way of using the addition and subtraction operators. According to this table, we are not allowed to add an “unsigned” value to a “signed” one. If we need to perform this type of addition, we will have to first type cast one of the operands to the appropriate type. What about adding a “signed” or “unsigned” value to a “1” or “0” represented by a “std_logic” signal? As listed in the above table, this operation is allowed. Why is this case important? Consider implementing an adder with input carry . Since we are allowed to have an operand of type “std_logic”, we can simply declare the input carry to be of type “std_logic” and add it to the adder’s input vectors, which are declared as two “signed”/“unsigned” objects. You can also use this capability to efficiently implement “a conditional incrementer”. See Example 9.4 of this book to learn more about this interesting application.

“Signed”/“Unsigned” Addition without Overflow

As mentioned above, we can increase the length of signals by one bit if we want to prevent overflow. For example, when dealing with “unsigned” objects, we can use the following code:

Since the input ports represent an unsigned value, we can append a zero after the most significant bit position of the operands without altering the represented values. This can be achieved using the concatenation operator , &, as in line 10 of the above code. In this way, we are resizing the operands to be five-bit vectors. Since the addition operation preserves the data path width, the sum will be represented using a five-bit unsigned number which is assigned to out1 in this example. Figure 3 shows an ISE simulation of this code.

When working with signed numbers, we can sign-extend the operands using the concatenation operator. The following code shows how we can avoid overflow in this case.

In this case, the ports represent “signed” numbers, so we should duplicate the sign bit rather than append zeros after the MSB.

Unlike the addition operator, the multiplication operator (*) does not preserve the data path width. The bit-width of the product is equal to the sum of the bit-widths of the two operands. For example, when multiplying an eight-bit number by a four-bit one, the result will be twelve bits long. Hence, in this case there is no overflow. However, we will generally have to truncate the result somewhere in our calculations to ensure that the data path does not become excessively wide.

• The “signed” and “unsigned” data types are vectors of elements of type “std_logic”.
• We can assign an element of a “signed”/“unsigned” vector to a “std_logic” object.
• Numeric operations are generally defined such that the data path width does not change.
• We can prevent overflow when performing addition by increasing by one bit the length of the input signals.
• It’s important to know what data types can be used as the operands of a given operator.
• Unlike the addition operator, the multiplication operator (*) does not preserve the data path width. The bit-width of the product is equal to the sum of the bit-widths of the two operands.

To see a complete list of my articles, please visit  this page .

Related Content

• VHDL Data Types: Some Classifications and the Enumerated Type
• Simplifying VHDL Code: The Std_Logic_Vector Data Type
• Integer and Its Subtypes in VHDL
• Concurrent Conditional and Selected Signal Assignment in VHDL
• MEAN WELL Enclosed Type Power Supplies | Digital Datasheet
• Understanding Different Types of Electrical Signals: Analog & Digital

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Designing Circuits with VHDL

1. introduction, 2. combinational circuits, signal assignments in vhdl.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullAdder is     port(  A,B: in  std_logic;  -- input bits for this stage            Ci:   in  std_logic; -- carry into this stage            S:    out std_logic; -- sum bit            Co:   out std_logic  -- carry out of this stage     ); end fullAdder; architecture a1 of fullAdder is begin     S <= A xor B xor Ci;     Co <= (A and B) or ((A xor B) and Ci); end a1;

Processes and Conditional Statements

if a = '0' then     x <= a;     y <= b; elsif a = b then     x <= '0';   y <= '1'; else     x <= not b; y <= not b; end if;

Every signal that is assigned a value inside a process must be defined for all possible conditions.

Case Statements

Structural vhdl, 3. sequential circuits.

busy   is high when the circuit is in the middle of performing an operation;             while busy is high, the insert and delete inputs are ignored; the             outputs are not required to have the correct values when busy is high empty     is high when there are no pairs stored in the priority queue; delete             operations are ignored in this case full      is high when there is no room for any additional pairs to be stored;             insert operations are ignored in this case

• For adjacent pairs in the bottom row, the pair to the left has a key that is less than or equal to that of the pair on the right.
• For pairs that are in the same column, the key of the pair in the bottom row is less than or equal to that of the pair in the top row.
• In both rows, the empty blocks (those with dp =0) are to the right and either both rows have the same number of empty blocks or the top row has one more than the bottom row.

entity priQueue is     Port (clk, reset : in std_logic;           insert, delete : in std_logic;           key, value : in std_logic_vector(wordSize-1 downto 0);           smallValue : out std_logic_vector(wordSize-1 downto 0);           busy, empty, full : out std_logic     );    end priQueue; architecture a1 of priQueue is constant rowSize: integer := 4; -- local constant declaration type pqElement is record     dp: std_logic;     key: std_logic_vector(wordSize-1 downto 0);     value: std_logic_vector(wordSize-1 downto 0); end record pqElement; type rowTyp is array(0 to rowSize-1) of pqElement; signal top, bot: rowTyp; type state_type is (ready, inserting, deleting); signal state: state_type; begin     process(clk) begin         if rising_edge(clk) then             if reset = '1' then                 for i in 0 to rowSize-1 loop                     top(i).dp <= '0'; bot(i).dp <= '0';                 end loop;                 state <= ready;             elsif state = ready and insert = '1' then                 if top(rowSize-1).dp /= '1' then                     for i in 1 to rowSize-1 loop                         top(i) <= top(i-1);                     end loop;                     top(0) <= ('1',key,value);                     state <= inserting;                 end if;             elsif state = ready and delete = '1' then                 if bot(0).dp /= '0' then                     for i in 0 to rowSize-2 loop                         bot(i) <= bot(i+1);                     end loop;                     bot(rowSize-1).dp <= '0';                     state <= deleting;                 end if;             elsif state = inserting or state = deleting then                 for i in 0 to rowSize-1 loop                     if top(i).dp = '1' and                         (top(i).key < bot(i).key                          or bot(i).dp = '0') then                         bot(i) <= top(i); top(i) <= bot(i);                     end if;                end loop;                 state <= ready;             end if;         end if;     end process;     smallValue <= bot(0).value when bot(0).dp = '1' else                   (others => '0');     empty <= not bot(0).dp;     full <= top(rowSize-1).dp;     busy <= '1' when state /= ready else '0'; end a1;

4. Functions and Procedures

package commonConstants is     constant lgWordSize: integer := 4;        constant wordSize: integer := 2**lgWordSize; end package commonConstants; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commonConstants.all; entity firstOne is     Port (a: in std_logic_vector(0 to wordSize-1);           x: out std_logic_vector (lgWordSize downto 0)      ); end firstOne; architecture a1 of firstOne is procedure encode(x: in std_logic_vector(0 to wordSize-1);                 indx: out std_logic_vector(lgWordSize-1 downto 0);                 errFlag: out std_logic) is -- Unary to binary encoder. -- Input x is assumed to have at most a single 1 bit. -- Indx is equal to the index of the bit that is set. -- If no bits are set, errFlag bit is made high. -- This is conceptually simple. -- --        indx(0) is OR of x(1),x(3),x(5), ... --        indx(1) is OR of x(2),x(3), x(6),x(7), x(10),x(11), ... --        indx(2) is OR of x(4),x(5),x(6),x(7), x(12),x(13),x(14(,x(15),... -- -- but it's tricky to code so it works for different word sizes. type vec is array(0 to lgWordSize-1) of std_logic_vector(0 to (wordSize/2)-1); variable fOne: vec; variable anyOne: std_logic_vector(0 to wordSize-1); begin     -- fOne(0)(j) is OR of first j bits in x1,x3,x5,...     -- fOne(1)(j) is OR of first j bits in x2,x3, x6,x7, x10,x11,...     -- fOne(2)(j) is OR of first j bits in x4,x5,x6,x7, x12,x13,x14,x15,...     for i in 0 to lgWordSize-1 loop         for j in 0 to (wordSize/(2**(i+1)))-1 loop                        for h in 0 to (2**i)-1 loop                 if j = 0 and h = 0 then                     fOne(i)(0) := x(2**i);                 else                     fOne(i)((2**i)*j+h) := fOne(i)((2**i)*j+h-1) or                                            x(((2**i)*(2*j+1))+h);                 end if;             end loop;         end loop;         indx(i) := fOne(i)((wordSize/2)-1);     end loop;     anyOne(0) := x(0);     for i in 1 to wordSize-1 loop         anyOne(i) := anyOne(i-1) or x(i);     end loop;     errFlag := not anyOne(wordSize-1); end procedure encode; function firstOne(x: std_logic_vector(0 to wordSize-1))                         return std_logic_vector is -- Returns the index of the first 1 in bit string x. -- If there are no 1's in x, the value returned has a -- 1 in the high order bit. variable allZero: std_logic_vector(0 to wordSize-1); variable fOne: std_logic_vector(0 to wordSize-1); variable rslt: std_logic_vector(lgWordSize downto 0); begin     allZero(0) := not x(0);     fOne(0) := x(0);     for i in 1 to wordSize-1 loop         allZero(i) := (not x(i)) and allZero(i-1);         fOne(i) := x(i) and allZero(i-1);     end loop;     encode(fOne,rslt(lgWordSize-1 downto 0),rslt(lgWordSize));     return rslt; end function firstOne; begin     x <= firstOne(a); end a1;

5. Closing Remarks

Variables vs. Signals in VHDL

Variables and Signals in VHDL appears to be very similar. They can both be used to hold any type of data assigned to them. The most obvious difference is that variables use the := assignment symbol whereas signals use the <= assignment symbol. However the differences are more significant than this and must be clearly understood to know when to use which one. If you need a refresher, try this page about VHDL variables .

Signals vs. Variables:

• Variables can only be used inside processes, signals can be used inside or outside processes.
• Any variable that is created in one process cannot be used in another process, signals can be used in multiple processes though they can only be assigned in a single process .
• Variables need to be defined after the keyword process but before the keyword begin . Signals are defined in the architecture before the begin statement.
• Variables are assigned using the := assignment symbol. Signals are assigned using the <= assignment symbol.
• Variables that are assigned immediately take the value of the assignment. Signals depend on if it’s combinational or sequential code to know when the signal takes the value of the assignment.

The most important thing to understand (and the largest source of confusion) is that variables immediately take the value of their assignment, whereas signals depend on if the signal is used in combinational or sequential code . In combinational code, signals immediately take the value of their assignment. In sequential code, signals are used to create flip-flops, which inherently do not immediately take the value of their assignment. They take one clock cycle. In general, I would recommend that beginners avoid using variables. They can cause a lot of confusion and often are hard to synthesize by the tools.

The example below demonstrates how signals behave differently than variables. Notice that r_Count and v_Count appear to be the same, but they actually behave very differently.

Variables can be a bit tricky to display in simulation. If you are using Modelsim, read more about how to see your variables in Modelsim’s waveform window . Look carefully at the waveform above. Do you see how o_var_done pulses every 5th clock cycle, but o_sig_done pulses every 6th clock cycle? Using signals and variables to store data generates very different behavior . Make sure you clearly understand what you code will be generating and make sure that you simulate your code to check that behaves like you want!

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courses:system_design:vhdl_language_and_syntax:sequential_statements:variables

Fundamentals

• Name within process declarations
• Known only in this process
• Immediate assignment
• Keep the last value
• Signal to variable
• Variable to signal
• Types have to match

Variables can only be defined in a process and they are only accessible within this process.

Variables and signals show a fundamentally different behavior. In a process, the last signal assignment to a signal is carried out when the process execution is suspended. Value assignments to variables, however, are carried out immediately. To distinguish between a signal and a variable assignment different symbols are used: ’⇐’ indicates a signal assignment and ’:=’ indicates a variable assignment.

Variables vs. Signals

• Signal values are assigned after the process execution
• Only the last signal assignment is carried out
• M ⇐ A; is overwritten by M ⇐ C;
• The 2nd adder input is connected to C

The two processes shown in the example implement different behavior as both outputs Z and Y will be set to the result of B+C when signals are used instead of variables.

Please note that the intermediate signals have to added to the sensitivity list, as they are read during process execution.

Use of Variables

• signal to variable assignment
• execution of algorithm
• variable to signal assignments
• no access to variable values outside their process
• variables store their value until the next process call

Variables are especially suited for the implementation of algorithms. Usually, the signal values are copied into variables before the algorithm is carried out.

The result is assigned to a signal again afterwards.

Variables keep their value from one process call to the next, i.e. if a variable is read before a value has been assigned, the variable will have to show storage behavior. That means it will have to be synthesized to a latch or flip flop respectively.

Variables: Example

• Parity calculation
• Synthesis result:

In the example a further difference between signals and variables is shown. While a (scalar) signal can always be associated with a line, this is not valid for variables. In the example the for loop is executed four times. Each time the variable TMP describes a different line of the resulting hardware. The different lines are the outputs of the corresponding XOR gates.

Shared Variables (VHDL’93)

• Accessible by all processes of an architecture (shared variables)
• Can introduce non determinism

In VHDL 93, global variables are allowed.

These variables are not only visible within a process but within the entire architecture.

The problem may occur, that two processes assign a different value to a global variable at the same time. It is not clear then, which of these processes assigns the value to the variable last.

This can lead to a non deterministic behavior!

In synthesizable VHDL code global variables must not be used.

Chapters of System Design > VHDL Language and Syntax > Sequential Statements

• Sequential Statements
• IF Statement
• CASE Statement
• WAIT Statement

Chapters of System Design > VHDL Language and Syntax

• General Issues
• VHDL Structural Elements
• Process Execution
• Extended Data Types
• Subprograms
• Subprogram Declaration and Overloading
• Concurrent Statements

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Signal assignment type

What is the meaning of "combinational assignment" and "registered assignment" to signals? In particular what are the differences between these two types of assignments?

• state-machines

2 Answers 2

Essentially, the difference boils down to whether the signal gets assigned on a clock edge or not.

Combinational code, like A <= B + 1 would have A being assigned B+1 "immediately," whereas

would result in A being assigned B+1 only on a rising clock edge. With code like this, other blocks can use the value of A being guaranteed that its value will be stable and unchanging after a clock edge.

Registers, or clock gating in general I suppose, are really what make designs of any complication possible. You create a pipeline of operations by putting a register at the border between operations. For example, the input operands to an ALU must be stable - in a register- so that the ALU can execute properly, and the result of the ALU's execution should be in a register so that whatever block uses it does not 'see' the changing values inside the ALU as the calculations take place, but only the stable last result.

• \$\begingroup\$ Question: Is a transparent latch considered combinatorial or registered? \$\endgroup\$ –  The Photon Commented May 14, 2012 at 4:52
• \$\begingroup\$ Yes and no - the input to a transparent latch propagates directly to the output, not on a clock edge. But the addition of an enable signal could make the latch be controlled on a clock edge, ie, opaque. \$\endgroup\$ –  Kevin H Commented May 14, 2012 at 16:17

Assignments in VHDL are neighter specified as registered or combinatorial. In VHDL the actual assignment type (the type of RTL logic generated) is just inferred.

Registers in VHDL are created explicitly by assigning a signal on a clock edge, though just because a process has a clock it does not mean all signals in that block will be assigned on every edge.

Also registers can be inferred without a clock, if some path through a process does not assign a signal, then VHDL assumes you meant to latch that signal between successive passes. This is called an inferred latch (and should be avoided).

VHDL does not know about the technology that you are going to be using. It does not know whether your synthisis engine can generate T,D,JK,SR, or any other sort of latch. For that reason it just suggests a latch, it is up to the synthisis enging to decide which latch fits the bill or if it is simply impossible. Similarlay the fitter might say that a particular latch requested by the synthisis enging is not available or there are no enough of them.

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VHDL assigning literals

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as:

But in my IDE (Quartus), I get a complaint "UNSIGNED type does not match integer literal." I also get complaints for adding numbers to types defined like this. Whats the preferred change I need to make?

• unsigned-integer

3 Answers 3

See other answers, and note that for non-zero literals, you probably want to do something like:

Substitute a literal for n . This works for n =0 too, of course, but it's not as tidy as (others => '0') .

• LCD_DATA'LENGTH isn't available until after the semicolon. IEEE Std 1076-1993 10.3 Notes "2—The rules defining immediate scope, hiding, and visibility imply that a reference to an identifier, character literal, or operator symbol within its own declaration is illegal (except for design units). The identifier, character literal, or operator symbol hides outer homographs within its immediate scope—that is, from the start of the declaration. On the other hand, the identifier, character literal, or operator symbol is visible only after the end of the declaration (again, except for design units)." –  user1155120 Commented Mar 18, 2014 at 23:02
• For -2008 that's Section 12.3 Visibility, same Note 2. –  user1155120 Commented Mar 18, 2014 at 23:16
• The original erroneous answer provided variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, LCD_DATA'length); Essentially something isn't available until it is declared and the declaration is variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression ] ; , which is where the after the semicolon comment comes from. See IEEE Std 1076-1993 4.3.1.3 (6.4.2.4 -2008) Variable declarations. –  user1155120 Commented Mar 18, 2014 at 23:26
• Yeah, I'm so used to using that construct in processes, etc., I forgot it was illegal in declarations. –  fru1tbat Commented Mar 19, 2014 at 13:53

And for the 2nd part of your question while adding number of this type.

Check whether you have used above libraries in the code or not.

unsigned is related to std_ulogic, where the value for an element would be '0'.

which provides an aggregate for the default assignment with all elements set to '0'.

You can't assign a single element of integer type to an array of std_ulogic elements.

You can add signed or unsigned to a natural (unsigned) or integer (signed) using "+" functions defined in package numeric_std:

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