assignment operator in verilog

System Verilog Operators: A Comprehensive Guide

Niranjana R

December 3, 2023

System Verilog operators : is a hardware description language used in the development and verification of digital circuits and systems. Similar to other programming languages, it has a set of operators that allow designers to perform various operations on the data. System Verilog operators are classified into different categories based on their functionality. Understanding these operators is crucial for designing efficient and error-free digital circuits.

The basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators. These operators are used to perform basic mathematical and logical operations, such as addition, subtraction, multiplication, division, and comparison, and logical operations like AND, OR, and NOT. Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators. These operators are used to perform complex operations on large data sets, such as data compression, encryption, and decompression.

Table of Contents

Key Takeaways

• System Verilog operators are used in the development and verification of digital circuits and systems.
• Basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators.
• Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators.

Basic System Verilog Operators

In System Verilog, operators are essential building blocks for designing digital circuits. These operators allow us to perform various operations on digital data and manipulate it to achieve the desired output. In this section, we will discuss the three basic types of operators: Arithmetic, Relational, and Logical.

Arithmetic Operators

Arithmetic operators are used to perform mathematical operations on operands. The basic arithmetic operators in System Verilog are:

For example, the expression a = b + c adds the values of b and c and stores the result in a.

Relational Operators

Relational operators are used to compare two operands. The result of a relational operator is either true or false. The relational operators in System Verilog are:

For example, the expression if (a == b) compares the values of a and b and executes the code inside the if statement if they are equal.

Logical Operators

Logical operators are used to perform logical operations on operands. The logical operators in System Verilog are:

For example, the expression if (a && b) checks if both a and b are true and executes the code inside the if statement if they are.

Understanding these basic operators is essential for designing digital circuits in System Verilog. By using these operators, we can perform various operations on digital data and manipulate it to achieve the desired output.

Advanced System Verilog Operators

In addition to the basic operators, System Verilog provides advanced operators to perform complex operations. These operators are an essential part of System Verilog and are widely used in the development of digital circuits. In this section, we will discuss two of the most important advanced operators: Bitwise Operators and Shift Operators.

Bitwise Operators

Bitwise operators are used to manipulate individual bits of a variable. System Verilog provides six bitwise operators: AND, OR, XOR, NAND, NOR, and XNOR. These operators can be used to perform various operations such as masking, setting, and clearing bits.

Shift Operators

Shift operators are used to shift the bits of a variable left or right. System Verilog provides four shift operators: left shift, right shift, arithmetic right shift, and logical right shift. These operators are used to perform various operations such as multiplication and division by powers of two.

In summary, bitwise and shift operators are essential in System Verilog for manipulating individual bits and shifting bits left or right. By using these advanced operators, we can perform complex operations with ease and efficiency.

Assignment Operators in System Verilog

In System Verilog, we use assignment operators to assign values to variables. The most commonly used assignment operator is the “=” operator. We use this operator to assign a value to a variable. For example, if we want to assign the value of 5 to a variable named “a” , we would write “a = 5;” .

System Verilog also provides us with other assignment operators that we can use to perform certain operations on variables while assigning values to them. These operators are listed in the table below:

By using these assignment operators, we can perform operations on variables and assign the result to the same variable in a single statement. This makes our code more concise and easier to read.

Conditional Operators in System Verilog

In System Verilog, conditional operators are used to create conditional expressions. They are a shorthand way to write if/else statements. The conditional operator is also known as the ternary operator because it takes three operands. The syntax of the conditional operator is as follows:

The conditional operator evaluates the condition first. If the condition is true, it evaluates the expression immediately after the question mark. If the condition is false, it evaluates the expression immediately after the colon.

One of the advantages of using the conditional operator is that it makes the code more concise and easier to read. It can also be used in assignments, which can help reduce the number of lines of code.

Another conditional operator in System Verilog is the implication operator. The implication operator is used to create logical implications. It takes two operands and returns a Boolean value. The syntax of the implication operator is as follows:

The implication operator returns true if the condition is false or if both the condition and the expression are true. It returns false if the condition is true and the expression is false.

In summary, System Verilog provides two types of conditional operators: the conditional operator and the implication operator. These operators can help reduce the number of lines of code and make the code more concise and easier to read.

Miscellaneous Operators in System Verilog

In addition to the basic arithmetic, relational, and logical operators, System Verilog provides several miscellaneous operators that can be used in digital circuit design.

Replication Operator

The replication operator {} is used to replicate a single value or a set of values multiple times. The syntax for the replication operator is {N{value}}, where N is the number of times the value is replicated.

For example, {8{1’b0}} represents a vector of eight bits, all set to 0. This operator is useful when designing circuits that require a large number of identical components.

Concatenation Operator

The concatenation operator {} is used to concatenate two or more vectors into a single vector. The syntax for the concatenation operator is {vector1, vector2, …, vectorN}, where vector1 through vectorN are the vectors being concatenated.

For example, {a, b} represents a vector that is the concatenation of vectors a and b. This operator is useful when designing circuits that require combining multiple vectors into a single vector.

Ternary Operator

The ternary operator ?: is a conditional operator that is used to assign a value to a variable based on a condition. The syntax for the ternary operator is condition ? true_value : false_value, where condition is the condition being evaluated, true_value is the value assigned if the condition is true, and false_value is the value assigned if the condition is false.

For example, y = (x>0) ? 1 : 0 assigns the value 1 to y if x is greater than 0, and assigns the value 0 to y if x is less than or equal to 0. This operator is useful when designing circuits that require conditional assignments.

Bit-select and Part-select Operators

The bit-select operator [] and the part-select operator [start:end] are used to select a single bit or a range of bits from a vector, respectively. The syntax for the bit-select operator is vector[index], where vector is the vector being selected from and index is the index of the bit being selected. The syntax for the part-select operator is vector[start:end], where vector is the vector being selected from, start is the index of the starting bit, and end is the index of the ending bit.

For example, a[7:0] represents a vector that consists of the eight least significant bits of vector a. This operator is useful when designing circuits that require selecting specific bits or ranges of bits from a vector.

These operators, along with the basic operators, provide a powerful set of tools for designing digital circuits using System Verilog.

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Verilog Operators

Data that cannot be processed is quite useless, there'll always be some form of calculation required in digital circuits and computer systems. Let's look at some of the operators in Verilog that would enable synthesis tools realize appropriate hardware elements.

Verilog Arithmetic Operators

If the second operand of a division or modulus operator is zero, then the result will be X. If either operand of the power operator is real, then the result will also be real. The result will be 1 if the second operand of a power operator is 0 (a 0 ).

An example of how arithmetic operators are used is given below.

Verilog Relational Operators

An expression with the relational operator will result in a 1 if the expression is evaluated to be true, and 0 if it is false. If either of the operands is X or Z, then the result will be X. Relational operators have a lower precedence than arithmetic operators and all relational operators have the same precedence.

Verilog Equality Operators

Equality operators have the same precedence amongst them and are lower in precedence than relational operators. The result is 1 if true, and 0 if false. If either of the operands of logical-equality (==) or logical-inequality (!=) is X or Z, then the result will be X. You may use case-equality operator (===) or case-inequality operator (!==) to match including X and Z and will always have a known value.

Verilog Logical Operators

The result of a logical and (&&) is 1 or true when both its operands are true or non-zero. The result of a logical or (||) is 1 or true when either of its operands are true or non-zero. If either of the operands is X, then the result will be X as well. The logical negation (!) operator will convert a non-zero or true operand into 0 and a zero or false operand into 1, while an X will remain as an X.

Verilog Bitwise Operators

This operator will combine a bit in one operand with its corresponding bit in the other operand to calculate a single bit result.

Verilog Shift Operators

• Logical shift operators     :  and >>
• Arithmetic shift operators : and >>>

An Introduction to the Verilog Operators

In this post, we talk about the different operators which we can use in verilog. These operators provide us with a way to process the digital data in our verilog designs.

This processing can be extremely simple, as is the case with simple logic gates . However, we may also need to perform complex logical or mathematical operations on our data.

In any case, verilog provides us with a number of operators which allow us to perform a wide range of different calculations or operations on our data.

In most instances when we use verilog operators, we create boolean expressions or logic circuits which we want to synthesize . However, there are also some operators which we can't use to write synthesizable code.

Let's take a closer look at the various different types of operator which we can use in our verilog code.

• Verilog Bit Wise Operators

We use the bit wise operators to combine a number of single bit inputs into a single bit output. In addition, we can also use the bit wise operators on verilog vector types .

We most commonly use the bit wise operators to model logic gates in verilog.

The table below shows the full list of bit wise operators which we can use in verilog.

The verilog code below shows how we use each of these operators in practise.

• Verilog Arithmetic Operators

We use arithmetic operators to perform basic mathematic functions on our variables. These operators should already be familiar as they are mostly replications of common mathematic symbols.

However, these operators also require some consideration when we use them with synthesizable code.

The plus, minus and multiplication operators can all be synthesised by most modern tools.

However, this can often result in sub-optimal logical performance. As a result, it can be necessary to design logic circuits which specifically perform these functions.

Alternatively, we may wish to use DSP blocks within our FPGA to perform these operations more efficiently.

We should never use the modulus, exponential or divide operators for synthesizable code as most tools will be unable to handle them.

The table below shows the full list of arithmetic operators in Verilog.

The code snippet below shows how we use each of these operators in practise.

• Verilog Relational Operators

We use relational operators to compare the value of two different variables in verilog. The result of this comparison returns either a logical 1 or 0 , representing true and false respectively.

These operators are similar to what we would see in other programming languages such as C or Java .

In addition to this, most of these operators are also commonly used in basic mathematics expressions so they should already feel familiar.

The table below shows the full list of relational operators in Verilog.

The verilog code below shows how we use each of the relational operators in practise.

• Verilog Logical Operators

The verilog logical operators are similar to the bit-wise operators we have already seen.

However, rather than using these operators to model gates we use them to combine relational operators. As a result, we can build more complex expressions which can perform more than one comparison.

As with relational operators, these expressions return either a 1 (true) or 0 (false).

There are only three logical operators which we can use in verilog. Again, these are similar to operators which are used in languages such as C or Java.

The table below shows the full list of logical operators in Verilog.

The verilog code below shows how we use each of the logical operators in practise.

Again, it is important that we use parentheses to separate the different elements in our expressions when using these operators.

• Verilog Shift Operators

In addition to the operators we have already seen, there are a few extra operators which we can use for specific logical functions.

One of the most useful and commonly used of these special functions are the shift operators, which are shown in the table below.

When designing digital circuits, we frequently make use of shift operations . As a result, verilog provides us with a simple technique for implementing these functions.

The shift operator actually requires two arguments. The first of these is the name of the signal which we want to shift. The second argument is the number of bits we want to shift.

When we use the logical shift operators, all the blank positions are filled with 0b after the signal has been shifted by the required number of bits.

In contrast, the arithmetic shift operators preserve the sign of the shifted signal. As a result of this, they should only be used with the verilog signed types .

The code snippet below shows how we use the shift operators in practise.

• Verilog Conditional Operator

In verilog, we use a construct known as the conditional operator to assign data to a signal based on a conditional statement .

To use the conditional operator, we write a logical expression before the ? operator which is then evaluated to see if it is true or false.

The output is assigned to one of two values depending on whether the expression is true or false.

This operator may already be familiar as it is also used in other programming languages such as C and Java . However, in this case it is known as the ternary operator.

The code snippet below shows the general syntax for the verilog conditional operator.

When the expression given in the <condition> field evaluates as true, then the output is set to the value given in the <true> field.

If the conditional expression evaluates as false, then the output is set to the value given by the <false> field.

The code snippet below shows a practical example of the verilog conditional operator. In the a future post in this series, we see how we can use the conditional operator model multiplexors .

• Concatenation and Replication Operators

The final types of verilog operator which we can use are the concatenation and replication operators.

In both instances, the output of these operators are a vector type. However, the inputs to both of these operators can be either single bit or vector types.

Both of these verilog operators are show in the table below.

We use the verilog concatenation operator to combine two or more signals into a vector.

As an example, we may have 2 single bit signals which we want to combine to use as an address for a multiplexor.

To use the concatenation operator, we list the signals which we wish to combine within the curly brackets. We separate this list of signals using a comma.

When we use the verilog concatenation operator, the bits in the output match the order in which they are listed inside the brackets.

For example, the code snippet below would result in a output vector which has the value 0011b.

We use the replication operator to assign the same value to a number of bits in a vector.

For example, if we wanted to assign all of the bits of a vector to 0b then we would use the replication operator.

When we use the replication operator we have to specify both the signal or value we want to replicate and the number of times we want to replicate it.

The verilog code below show how we use the concatenation and replication operators in practice.

Which type of operators do we use to model logic gates in verilog?

We use the bit wise operators to model logic gates in verilog.

Two of the arithmetic operators should not be used with synthesizable code – name them.

The division and modulus operators can’t be synthesized.

What is the difference between the bit wise and logical operators?

The bit wise operators work on individual bits whereas the logical operators are used to combine logical expressions.

What is the difference between the logical shift operators and the arithmetic shift operators.

The logical shift operators pad the blank positions with 0b whereas the arithmetic operator preserves the sign of the signal.

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Assign Statement In Verilog

• You can use assign statement inside of module.
• You can use assign statement to output port and any wire declared inside the module

Examples of assign statement

In above example, y is output port and we are assigning this output port to a and b. It will create a and gate where a and b are inputs and y is output

In above example, we've descrived a NAND gate. We can use one statemetn but for better understanding we've use two statement to illustrate how we can use assign statement to both wire and output port. wire w is assign with a AND b, and output y is assigned not of wire w. This creates a NAND gate in verilog HDL.

In above example, we have described a full-adder using assign statement. Note that we can write complete boolean equation using assign statement

We can also use Verilog operators using assign statement. Below is the example of full-adder using assign statement and Verilog operator

In above example, we are using + operator, which addition operator in Verilog. We are assigning output sum and carry with addition of a, b and cin.

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Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following:

We normally have to reset flip-flops, thus every time the clock makes the transition from 0 to 1 (posedge), we check if reset is asserted (synchronous reset), then we go on with normal logic. If we look closely we see that in the case of combinational logic we had "=" for assignment, and for the sequential block we had the "<=" operator. Well, "=" is blocking assignment and "<=" is nonblocking assignment. "=" executes code sequentially inside a begin / end, whereas nonblocking "<=" executes in parallel.

I was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel. After all, you can make blocking assignments with assign statements outside of always blocks, and those all run in parallel. Is this a mistake, or is the behavior different inside an always block? And, if the behavior IS different inside an always block, can nonblocking assignments be made outside an always block?

3 Answers 3

was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel.

Blocking assignment executes "in series" because a blocking assignment blocks execution of the next statement until it completes. Therefore the results of the next statement may depend on the first one being completed.

Non-blocking assignment executes in parallel because it describes assignments that all occur at the same time. The result of a statement on the 2nd line will not depend on the results of the statement on the 1st line. Instead, the 2nd line will execute as if the 1st line had not happened yet.

• \$\begingroup\$ So what about assign statements? Are they just in a whole class of their own? \$\endgroup\$ –  Void Star Commented Nov 24, 2013 at 4:25
• 6 \$\begingroup\$ Yes, assign statements occur outside of always blocks and are generally used to describe to combinatorial (un-latched) logic (while always blocks, with some exceptions, describe sequential logic). AFAIK, assign statements always execute "in parallel" whenever their LHS has a value change. \$\endgroup\$ –  The Photon Commented Nov 24, 2013 at 4:28
• \$\begingroup\$ Okay... I'm starting to get the impression that Verilog just isn't the most elegantly designed language. This is gonna be like learning C was. \$\endgroup\$ –  Void Star Commented Nov 24, 2013 at 5:30
• 2 \$\begingroup\$ Verilog was designed to "describe" hardware that already exists. Using it as a language to design (synthesize) hardware is a hack. \$\endgroup\$ –  The Photon Commented Nov 24, 2013 at 6:02
• 6 \$\begingroup\$ if Verilog "like learning C" is a problem, take a look at VHDL. Some people have fairly strong preferences for one or the other. To some, VHDL is just too verbose. To me, it's much better thought out. (signal/variable assignment semantics are much clearer than blocking/non for example). stackoverflow.com/questions/13954193/… and sigasi.com/content/vhdls-crown-jewel You may prefer it or hate it. But it's worth a look. \$\endgroup\$ –  user16324 Commented Nov 24, 2013 at 10:20

Assign statements are neither "blocking" or "nonblocking", they are "continuous". The output of an assign statement is always equal to the specified function of it's inputs. "blocking" and "nonblocking" assignments only exist within always blocks.

A blocking assignment takes affect immediately it is processed. A nonblocking assignment takes place at the end of processing the current "time delta".

always blocks can be used to model either combinatorial or sequential logic (systemverilog has always_comb and always_ff to make this explicit). When modeling combinatorial logic it's usually more efficient to use = but it typically doesn't really matter.

When modelling sequential logic (e.g. always @(posedge clk) ) you normally use nonblocking assingments. This allows you to deterime the "state after the clock edge" in terms of "the state before the clock edge".

It is sometimes useful to use blocking assignments in sequential always blocks as "variables". If you do this then there are two key rules to bear in mind.

• Do not access a reg that is set with blocking assignments inside a sequential always block from outside the always block it is assigned in.
• Do not mix blocking and nonblocking assignments to the same reg.

Breaking these rules is likely to result in synthesis failures and/or behaviour differences between simulation and synthesis.

• \$\begingroup\$ ""Do not access a reg that is set with blocking assignments inside a sequential always block from outside the always block it is assigned in."" Can you please explain it? \$\endgroup\$ –  user125575 Commented Oct 4, 2016 at 6:44
• 2 \$\begingroup\$ Different sequential always blocks do not have a defined order. So reading a "reg" set with a blocking assingment in one always block from another always block will lead to unpredicable behaviour. \$\endgroup\$ –  Peter Green Commented Oct 4, 2016 at 15:23
• \$\begingroup\$ And even if it appears to work in simulation, a synthesis tool should look at that and say "nope". I use local regs for those intermediate vars, and make sure that they are always assigned to on every clock before being read, so that no 'storage' is implied. \$\endgroup\$ –  greggo Commented Mar 30, 2017 at 11:57
• \$\begingroup\$ IIRC at least in quartus it is only considered a warning not an error. \$\endgroup\$ –  Peter Green Commented Mar 30, 2017 at 11:59
• \$\begingroup\$ You should not be using nonblocking assignment in combinational logic, it can lock up the simulation. For more details, refer this answer: electronics.stackexchange.com/a/506047/238188 \$\endgroup\$ –  Shashank V M Commented Oct 5, 2020 at 14:55

The term Blocking assignment confuses people because the word blocking would seem to suggest time-sequential logic. But in synthesized logic it does not mean this , because everything operates in parallel .

Perhaps a less confusing term would be immediate assignment , which would still differentiate the intermediate results of combinational logic from the inputs to non-transparent memory elements (for example clocked registers), which can have delayed assignment .

From a legalistic standpoint, it all works out very nicely. You can, in fact, consider the = to be a blocking (time-sequential) operation even within always_comb sequences. However, the distinction between time-sequential and parallel makes absolutely no difference in this case because the always_comb block is defined to repeat until the instruction sequence converges on a stable state -- which is exactly what the hardware circuitry will do (if it meets the timing requirements).

The synthesizable subset of Verilog (and especially SystemVerilog) is extremely simple and easy to use -- once you know the necessary idioms. You just have to get past the clever use of terminology associated with the so-called behavioral elements in the language.

• \$\begingroup\$ In behavioral coding styles ( as compared to RTL ), the distinction between blocking and non-blocking can be relevant. In some cases, the synthesis tool may be able to infer functionally equivalent RTL from behavioral component designs. \$\endgroup\$ –  Brent Bradburn Commented Jul 21, 2015 at 17:28
• \$\begingroup\$ Of course the procedural mode of SystemVerilog, applicable especially to initial statements within program blocks, uses (time-sequential) blocking assignment exclusively. This is useful for testbench design, but generally not for RTL specification. \$\endgroup\$ –  Brent Bradburn Commented Dec 18, 2015 at 18:58

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Verilog Conditional Operator

Just what the heck is that question mark doing.

Have you ever come across a strange looking piece of Verilog code that has a question mark in the middle of it? A question mark in the middle of a line of code looks so bizarre; they’re supposed to go at the end of sentences! However in Verilog the ? operator is a very useful one, but it does take a bit of getting used to.

The question mark is known in Verilog as a conditional operator though in other programming languages it also is referred to as a ternary operator , an inline if , or a ternary if . It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). Let’s look at how it is used:

Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”. Depending on if this condition evaluates to true, the first expression is chosen. If the condition evaluates to false, the part after the colon is chosen. I wrote an example of this. The code below is really elegant stuff. The way I look at the question mark operator is I say to myself, “Tell me about the value in r_Check. If it’s true, then return “HI THERE” if it’s false, then return “POTATO”. You can also use the conditional operator to assign signals , as shown with the signal w_Test1 in the example below. Assigning signals with the conditional operator is useful!

Nested Conditional Operators

There are examples in which it might be useful to combine two or more conditional operators in a single assignment. Consider the truth table below. The truth table shows a 2-input truth table. You need to know the value of both r_Sel[1] and r_Sel[0] to determine the value of the output w_Out. This could be achieved with a bunch of if-else if-else if combinations, or a case statement, but it’s much cleaner and simpler to use the conditional operator to achieve the same goal.

Learn Verilog

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The input “r_Sel” must be reg type? Could it be wire type?

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?: conditional operator in Verilog

Compact conditional operators.

Many Verilog designs make use of a compact conditional operator:

A comman example, shown below, is an “enable” mask. Suppose there is some internal signal named a . When enabled by en== 1 , the module assigns q = a , otherwise it assigns q = 0 :

The syntax is also permitted in always blocks:

Assigned Tasks

This assignment uses only a testbench simulation, with no module to implement. Open the file src/testbench.v and examine how it is organized. It uses the conditional operator in an always block to assign q = a^b (XOR) when enabled, else q= 0 .

Run make simulate to test the operation. Verify that the console output is correct. Then modify the testbench to use an assign statement instead of an always block . Change the type of q as appropriate for the assign statement.

Turn in your work using git :

Indicate on Canvas that your assignment is done.

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Is the ++ operator in System Verilog blocking or non-blocking?

Good coding convention says that we should use blocking assignments in a combinational block, and non-blocking assignments in a sequential block. I want to use the ++ operator in a combinatorial block, but I don't know if it is blocking. So is this code:

equivalent to this:

I did look in the 1800-2012 standard but could not figure it out. An answer that points me to the appropriate section in the standard would be appreciated.

• system-verilog

According to section 11.4.2 of IEEE Std 1800-2012 , it is blocking.

SystemVerilog includes the C increment and decrement assignment operators ++i , --i , i++ , and i-- . These do not need parentheses when used in expressions. These increment and decrement assignment operators behave as blocking assignments.

• So is there a non-blocking equivalent to ++ or do we have to verbosely code:count_ones <= count_ones + 1; –  WestHamster Commented Jan 21, 2020 at 13:09
• @WestHamster I believe that is correct. val <= val+ 1; will occur on the event. At least, it is also well supported even if some standard does all an alternate in future. –  artless noise Commented Sep 23, 2022 at 18:18

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