verilog non blocking assignments

Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

Blocking vs. Nonblocking in Verilog

The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time. So for example in the C code below:

The second line is only allowed to be executed once the first line is complete. Although you probably didn’t know it, this is an example of a blocking assignment. One assignment blocks the next from executing until it is done. In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which.

<=     Nonblocking Assignment

=      Blocking Assignment

The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3. Now consider this code:

See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3 . The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.

Nonblocking and Blocking Assignments can be mixed in the same always block. However you must be careful when doing this! It’s actually up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a Flip-Flop or not. If it is possible that the signal will be read before being assigned, the tools will infer sequential logic. If not, then the tools will generate combinational logic. For this reason it’s best just to separate your combinational and sequential code as much as possible.

One last point: you should also understand the semantics of Verilog. When talking about Blocking and Nonblocking Assignments we are referring to Assignments that are exclusively used in Procedures (always, initial, task, function). You are only allowed to assign the reg data type in procedures. This is different from a Continuous Assignment . Continuous Assignments are everything that’s not a Procedure, and only allow for updating the wire data type.

Leave A Comment Cancel reply

Save my name, email, and website in this browser for the next time I comment.

Blocking and Non-blocking Assignment in Verilog

• Assignment is only done in procedural block(always ot initial block)
• Both combintational and sequential circuit can be described.
• Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

Click like if you found this useful

Add Comment

This policy contains information about your privacy. By posting, you are declaring that you understand this policy:

• Your name, rating, website address, town, country, state and comment will be publicly displayed if entered.
• Your IP address (not displayed)
• The time/date of your submission (displayed)
• Administrative purposes, should a need to contact you arise.
• To inform you of new comments, should you subscribe to receive notifications.
• A cookie may be set on your computer. This is used to remember your inputs. It will expire by itself.

This policy is subject to change at any time and without notice.

These terms and conditions contain rules about posting comments. By submitting a comment, you are declaring that you agree with these rules:

• Although the administrator will attempt to moderate comments, it is impossible for every comment to have been moderated at any given time.
• You acknowledge that all comments express the views and opinions of the original author and not those of the administrator.
• You agree not to post any material which is knowingly false, obscene, hateful, threatening, harassing or invasive of a person's privacy.
• The administrator has the right to edit, move or remove any comment for any reason and without notice.

Failure to comply with these rules may result in being banned from submitting further comments.

These terms and conditions are subject to change at any time and without notice.

Comments (1)

hey in blocking assignment do we get shift in data i dont think so . we get all values same and equal to d.

Please do not focus on the module name; focus on how the netlist is generated after the synthesis.

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

• Blocking Assignments
• Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

• Blocking assignments (=) are done sequentially in the order the statements are written.
• A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Non-Blocking assignments

• Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
• The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
• The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
• Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

For Synthesis (Points to Remember):

• One must not mix “<=” or “=” in the same procedure.
• “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
• “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

Spread the Word

• Click to share on Facebook (Opens in new window)
• Click to share on Twitter (Opens in new window)
• Click to share on LinkedIn (Opens in new window)
• Click to share on Pinterest (Opens in new window)
• Click to share on Tumblr (Opens in new window)
• Click to share on Pocket (Opens in new window)
• Click to share on Reddit (Opens in new window)
• Click to email a link to a friend (Opens in new window)
• Click to print (Opens in new window)

Related posts:

• Synthesis and Functioning of Blocking and Non-Blocking Assignments.
• Delay in Assignment (#) in Verilog
• Ports in Verilog Module
• Module Instantiation in Verilog

Post navigation

Leave a reply cancel reply.

Your email address will not be published. Required fields are marked *

Save my name, email, and website in this browser for the next time I comment.

Notify me of follow-up comments by email.

Notify me of new posts by email.

Non Blocking Proceduaral assignments

The non-blocking assignment statement starts its execution by evaluating the RHS operand at the beginning of a time slot and schedules its update to the LHS operand at the end of a time slot. Other Verilog statements can be executed between the evaluation of the RHS operand and the update of the LHS operand. As it does not block other Verilog statement assignments, it is called a non-blocking assignment.

A less than or equal to ‘<=’ is used as a symbol for the non-blocking assignment operator.

• If <= symbol is used in an expression then it is interpreted as a relational operator. 
• If <= symbol is used in an assignment then it is interpreted as a non blocking operator. 

How race around condition is resolved in a nonblocking assignment?

If a variable is used in LHS of blocking assignment in one procedural block and the same variable is used in RHS of another blocking assignment in another procedural block.

In this example, 

Since procedural blocks (both initial and always) can be executed in any order.

In a non-blocking assignment statement no matter what is the order of execution, both RHS of the assignments (y <= data and data <= y) are evaluated at the beginning of the timeslot and LHS operands are updated at the end of a time slot. Thus, race around condition is avoided as there is no dependency on execution order and the order of execution of these two statements can be said to happen parallelly.

Verilog procedural assignment guidelines

For a beginner in Verilog, blocking and non-blocking assignments may create confusion. If are used blindly, it may create race conditions or incorrect synthesizable design. Hence, it is important to understand how to use them. To achieve synthesized RTL correctly, Verilog coding guidelines for blocking and non-blocking assignments are mentioned below

• Use non-blocking assignments for modeling flip flops, latches, and sequential logic.
• Use blocking assignment to implement combinational logic in always block.
• Use non-blocking assignment to implement sequential logic in always block.
• Do not mix blocking and non-blocking assignments in single always block i.e. For the implementation of sequential and combination logic in a single ‘always’ block, use non-blocking assignments.
• Do not assign value to the same variable in the different procedural blocks.
• Use non-blocking assignments while modeling both combination and sequential logic within the same always block.
• Avoid using #0 delay in the assignments.

Verilog Tutorials

• Getting started with verilog
• Hello World
• Procedural Blocks
• Non-blocking assignments
• Simple counter
• Synthesis vs Simulation mismatch

verilog Procedural Blocks Non-blocking assignments

Fastest entity framework extensions.

A non-blocking assignment ( <= ) is used for assignment inside edge-sensitive always blocks. Within a block, the new values are not visible until the entire block has been processed. For example:

Notice the use of non-blocking ( <= ) assignments here. Since the first assignment doesn't actually take effect until after the procedural block, the second assignment does what is intended and actually swaps the two variables -- unlike in a blocking assignment ( = ) or assignments in other languages; f1 still has its original value on the right-hand-side of the second assignment in the block.

Got any verilog Question?

• Advertise with us
• Cookie Policy
• Privacy Policy

Get monthly updates about new articles, cheatsheets, and tricks.

Verification Guide

SystemVerilog NonBlocking assignment

Nonblocking assignment.

• non-blocking assignment statements execute in parallel
• In the non-blocking assignment, all the assignments will occur at the same time. (during the end of simulation timestamp)

Nonblocking assignment example

In the below example, a and b are initialized with values 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment values expected in a and b are 15 and 20 respectively. but these values will get assigned only after the simulation time-stamp.

Simulator Output:

Nonblocking assignment example-2

In the below example, a and b are initialized with value 10 and 15 respectively. x<=a+b and y<=a+b+x value of x is sum of a (10) and b (15). -> x=10+15=25. value of y is sum of a (10) ,b(15) and x (0) -> became at current simulation time-stamp value of x=0. new value will get assigned at the end of current time stamp, and new value will be available only after the current time-stamp). therefore y=10+15+0=25;

❮ Previous Next ❯

fpga系列 HDL: 05 阻塞赋值(=)与非阻塞赋值(＜=)

• 在Verilog硬件描述语言（HDL）中，信号的赋值方式主要分为两种：连续赋值和过程赋值。每种赋值方式有其独特的用途和语法，并适用于不同类型的电路描述。

1. 连续赋值（Continuous Assignment,assign 和=）

• 连续赋值 主要用于描述 组合逻辑 ，通常与 assign 关键字一起使用。它在顶层模块或过程块外部进行，用于对 wire 类型的信号赋值。

特点 ：

• 组合逻辑 ：连续赋值用于实现组合逻辑，表示输出信号始终等于表达式的值。
• 实时更新 ：当右边的表达式中的任何信号发生变化时，左边的信号会立即更新。
• 信号类型 ：通常用于 wire 类型信号。

示例 1 ：

示例 2 ：

2. 过程赋值（Procedural Assignment）

• 过程赋值 用于过程块（如 always 或 initial 块）内，适用于描述 组合逻辑或时序逻辑 。过程赋值可以进一步分为两种：阻塞赋值（ = ）和非阻塞赋值（ <= ）。

2.1 阻塞赋值（Blocking Assignment， = ）

• 顺序执行 ：阻塞赋值按书写顺序执行，一个语句必须在前一个语句完成后才能执行下一个语句。
• 阻塞行为：在赋值完成之前，后续的语句不会执行。相当于“阻塞”了后续操作。
• 主要用于组合逻辑 ：通常用于描述组合逻辑，在 always @(*) 块中使用。

示例 ：

• 这个代码，阻塞赋值与下边的非阻塞赋值电路一样

ISE的RTL Schematic

vivado的 Schematic

ISE的Technology Schematic

2.2 非阻塞赋值（Non-blocking Assignment， <= ）

• 并行执行 ：非阻塞赋值允许赋值操作并行执行，不必等待前一个语句完成。
• 主要用于时序逻辑 ：通常用于描述时序逻辑，在 always @(posedge clk) 块中使用。

更换两句的顺序电路图没有改变

连续赋值 vs. 过程赋值 ：

• 连续赋值 ：用于 wire 类型信号，描述组合逻辑。
• 过程赋值 ：用于 reg 或 integer 等类型信号，描述组合或时序逻辑。

阻塞赋值 vs. 非阻塞赋值 ：

• 阻塞赋值 ：用于组合逻辑，按顺序执行，通常在 always @(*) 块中。
• 非阻塞赋值 ：用于时序逻辑，并行执行，通常在 always @(posedge clk) 块中。
• https://www.bilibili.com/video/BV1va411c7Dz?p=11

“相关推荐”对你有帮助么？

请填写红包祝福语或标题

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。 2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。