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How to assign a hex or decimal value to a std_logic_vector of length19 bits?

• Thread starter gabor
• Start date Dec 5, 2008
• Dec 5, 2008

I write almost exclusively Verilog code, but I inherited a VHDL project and I need to make some changes to it. I'm trying to make this human-readable, but I'm not versed with VHDL, so I have no clue even what to look this up under: This code works, but it is not very readable: signal flash_addr_i : std_logic_vector (18 downto 0) ; .. . . elsif ((flash_addr_i < 128) and write_flag = '1') then -- How can a human being make sense of of this? -- and why is 128 OK for the comparison above and not -- for the assignment below? flash_addr_i <= "0000000000010000000"; end if; .. . . I want to say: flash_addr_i <= 128; But then I get messages about flash_addr_i is not compatible with with type of 128. and if I try a hex constant like: flash_addr_i <= x"00080"; I get bit width mis-match problems. How can I write the equivalent of the Verilog: flash_addr_i <= 19'd128; or flash_addr_i <= 19'h80; I can't believe there's no way to do this in VHDL? Stumped, Gabor  

I write almost exclusively Verilog code, Click to expand...

I want to say:  flash_addr_i <= 128; Click to expand...

I can't believe there's no way to do this in VHDL? Click to expand...

Sadly, I doubt that. In gabor's code we see... So it seems fair to assume that the poor devil is saddled with old code that uses std_logic_unsigned instead of numeric_std. CONV_STD_LOGIC_VECTOR is what he needs. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK (e-mail address removed):// www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. Click to expand...

Gabor, signal   flash_addr_i            : std_logic_vector (18 downto 0) ; In VHDL-2008 (standardized, but not necessarily implemented yet) you can do:    flash_addr_i <= 19D"128";    flash_addr_i <= 19h"80"; For now you are stuck with:    flash_addr_i <= "000" & h"0080"; Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis    SynthWorks VHDL Training     http://www.synthworks.com A bird in the hand may be worth two in the bush, but it sure makes it hard to type. Click to expand...

Gabor,> I tried the 2008 standard stuff.  XST 10.1 doesn't support Did you try my other suggestion (it is not new stuff): flash_addr_i <= "000" & h"0080"; Yes this is operator overloading. Keep these a binary strings - unfortunately until vhdl-2008, the case statements are intolerant of "&" and expressions. Not a good thing if the rest of your project team is using VHDL. Probably ought to invest in training instead.  VHDL is quite simple once you get past the initial learning stuff. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis    SynthWorks VHDL Training     http://www.synthworks.com A bird in the hand may be worth two in the bush, but it sure makes it hard to type. Click to expand...

• Dec 6, 2008

There is no project "team" at this company or in other words, I am the team. Click to expand...

• Dec 30, 2013

hexadecimal to std_logic_vector Hello, someone help me please I have a signal z receives in hexadecimal,and this signal have multi value,I want to convert to binary, I use this syntax for example, convert the value 15 D(7 DOWNTO 0) <= to_stdlogicvector(x"15"); but I what I want is to convert SEVERAL value for example, a signal b I use it but it does not work ARCHITECTURE exo OF hex IS signal b : integer range 0 to 65535 ; BEGIN b <= (r*10/5) ; D(7 DOWNTO 0) <= to_stdlogicvector(x"b"); END exo; can someone help me  

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Understanding VHDL

Table of contents, 1. vhdl hardware description language, 2. design styles, 3. vhdl abstraction levels, 4. structure of vhdl modules, 5. vhdl data types, 6. vhdl variables, signals, constants, 7. vhdl operators, basics, structure, data types and operators.

Hardware description languages (HDL) are used to design digital and electronic systems. Today, the languages most widely employed are VHDL and Verilog. These description languages allow the user to write a program that describes the behavior of the circuit. This program can be used to simulate the operation of the circuit. And its implementation can be synthesized in a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or an Application Specific Integrated Circuit (ASIC).

VHDL stands for Very High-Speed Integrated Circuit Hardware Description Language and is what its name implies: a hardware description language. It is based on the ADA software programming language; the syntax is similar, but the way it behaves is different. VHDL models, describes, and simulates digital or electronic circuits and systems. Although VHDL and sequential programming languages (e.g., C / C++) look similar, VHDL handles sequential and concurrent executions. It also incorporates timing specifications (gate delays). Using an Electronic Design Automation (EDA) tool, a high-level VHDL behavioral model can be translated into a gate level netlist which describes the circuit in terms of gates and connections between them. The netlist is placed and routed to generate a layout. This layout created by the EDA tools is sometimes used to produce the electronic systems.

VHDL has many advantages:

• it supports design methodologies like top-down and bottom-up approaches,
• it provides a flexible design language,
• it allows a detailed implementation and a better design management,
• it has support for multi-level abstraction,
• it strongly supports code reusability and sharing.

Hardware description languages use two design methods: bottom-up or top-down. Nowadays, a hardware design uses both methodologies to implement a structure. In a top-down design approach, the designer adds details as the design progresses. First, he defines the top-level block and moves down to the smallest elements. Like a tree, the design starts from the roots (top-level block) and adds branches with the sub-blocks necessary to build the top-level.

The bottom-up methodology uses the smallest details to build the blocks, after which these blocks are used to create larger blocks. Thus, the top-level is built using blocks that are getting more and more abstract as the code is added. Top-down and bottom-up workflows are frequently combined. The top-level block's parameters are determined by the design architects. Logic developers divide the functionality into blocks and sub-blocks to determine how the design should be organized. Circuit designers are creating optimized circuits leaf-level cells. These leaf cells are then used to create higher-level cells. The logic-level designers start to design from the top and move down until all modules are defined in terms of leaf cells. The flow meets at this intermediate point, where the switch-level circuit designers have created a library of leaf cells using switches.

When discussing the various levels of abstraction in VHDL, it is all about the different styles of description. Thus, there are 3 major levels: behavioral, structural, and dataflow.

At this level, the model is represented by a functional description and is employed at the beginning of a design to be able to run a simulation. It is used mostly in test-bench design, because in the test-bench phase it is not so relevant if the hardware is achievable. Compared to other levels, behavioral is considered the highest abstraction level. At this level, a system is described in an algorithmic mode and does not imply a gate-level implementation. The behavioral level comprises one or more process statements, and each contains one or more sequential statements. In a simulator, all the statements are executed sequentially, similar to a conventional programming language.

Behavioral modeling uses sequential statements to describe a behavior of an entity. This makes it very similar to high-level programming languages, like C, C++, or JAVA. “Process” statements and various sequential statements are used to write this behavioral model. In VHDL, the descriptions of all processes are executed concurrently, but the statements included in the process description are executed sequentially.

A process label is just a name for a particular process. Assigning labels is especially useful while writing large pieces of code. They are not required, and their absence will not create any errors. A so called “sensitivity list” identifies all the signals by their name that the process is sensitive to. This list is optional, but without it, a process will run forever, unless a wait statement is included at the end of a process.

Example: 2-to-1 Multiplexer in behavioral modeling style.

The mode of operation of the multiplexer is declared in the architectural body, where the multiplexer sends the input signal from the user-specified address to its output. For the process to work properly, it must monitor the input ports. For this reason, the sensitivity list contains all three ports. Using IF … ELSIF statements, the multiplexer functionality can be created, and all these statements are running sequentially.

VHDL structural modeling is similar to doing a schematic design, but it uses text instead of block diagrams elements. This type of modeling has several advantages when it comes to large and complicated projects. Using a structural style, a big project can be split into two or more simple designs to make it easier to handle the complexity of the project. This allows to pack low-level functionality into modules. This way, already implemented modules can be reused without having to rewrite the design from scratch. In order to use this level of abstraction, one or more components need to be instantiated inside a design. For this, one or more architecture declarations need to be created. An architecture contains two parts, the declarative part and the statement section. In the declarative part, a component is declared with the ports that it uses. The statement section describes the way the ports interact with each other.

Example: 2 gates, AND & OR, connected in series

In this code, the output of an AND2 gate is linked to one of the inputs of an OR2 gate and compared with another signal.

VHDL dataflow modeling follows the way the data flows through the design, from input to output. This abstraction level specifies the functionality of a design without specifying its structure. This involves the description at a gate level of the appropriate logic gates (AND, OR, XOR, etc.). The dataflow uses one or more signal assignment statements. They can be used sequentially or in parallel. For this level, sequential designs are used, the output depends on the input and the previous states. Therefore, “memories” need to be used for the system designs.

For this abstraction level, several ways to implement a design are possible:

• concurrent signal assignments,
• conditional signal assignments,
• selected signal assignments.

For example, a multiplexer is a combinational circuit that selects, based on selection lines, one out of several inputs and sends it directly to the output. The table illustrates the truth table for a 4×1 multiplexer. Here, the Y column is the output with the selected port.

Example: Multiplexer using conditional signal assignment

Example: Multiplexer using selected signal assignment

VHDL Libraries and Packages

Libraries are a collection of packages that define the operators and operations in the logic utilized to describe a digital system. The IEEE library is commonly used; it defines a binary representation consisting of values of 0 and 1, and a standard logic representation (std_logic) with nine distinct logic values, of which the most important are: 0, 1, X (unknown) and Z (high impedance). To include a library in VHDL, the reserved word library is used in an instruction of this form:

Packages are a collection of elements, like data types, subprograms, constants, or operators, within a library. The reserved word for the inclusion of a package from a library is use, the instruction is written as:

For the IEEE library, to use the logic primitive’s description, it is required to include the package IEEE.std_logic_1164. For this, write the following code sequence:

VHDL Modules

The declaration for interface-signal uses this form:

• mode – indicates the direction of the signal: in, out, inout, buffer.
• in – carries information into the module, can be read but not updated in the module
• out – carries information out of the module, can be updated but not be read inside a module
• inout – can be read and updated, this mode is bidirectional
• buffer – carries information out of a module, and can be both updated and read from the module
• type – indicates the signal type: bit, boolean, std_logic, integer, real, character, time
• optional : a default value

For example, the next lines of code are the declaration for the entity of an and-gate with two inputs and one output:

The architecture descriptor – architecture – describes the function of the digital circuit. In this part of a module, one or more abstraction level presented above are combined to create an architecture. The code can set out how the circuit behaves using functional blocks and the connection between them, or a mathematical description of the logical functions (truth table, transition diagram, algorithm). The declaration of an architecture uses this form:

In the declaration, the signals and constants are assigned if they are needed. To describe logical primitives, the body of VHDL module architectures consists of:

• assignment operators:
• fundamental logic operators (not, and, or, nand, nor, xor, xnor)

Example: The and-gate architecture with two inputs described with fundamental logic and is:

VHDL Module Instantiation

Module instantiation is used to connect circuit elements. At the top level, the connection is made between modules, and the EDA tool creates the netlist for all the components and connections that are used. A VHDL design description written exclusively with component instantiation is known as “Structural VHDL”. This method is very similar to the schematic entry; in this case, instead of using graphic elements, it is implemented as text. One or more components can be declared in the architecture body. To instantiate a component inside a design, the following two steps are needed:

• declare the components in the declarative part of the architecture, and
• instantiate the component in the architecture statement section.

The declaration section of the architecture is included between the keyword “is” and “begin”:

For example, to instantiate the and-gate with two outputs modules in another architectural model, the simplest way is to copy the entity of and2 and paste it to the architectural body. After that, change the “entity” to “component”.

• Predefined data types:

* users defined data, for example, enumeration:

VHDL is a strongly typed language, so different data types cannot be combined in the same instruction.

Vector Types

When designing with a hardware description language, data buses are often used. Data buses comprise multiple bit buses. The data types presented above allow single bits to be modeled in a design. A vector consists of one or more bits that are modeled similarly to one of the predefined data. The most basic and encountered types of vectors in VHDL are made up of several bit or std_logic types. The code below is an example of how to declare a vector type signal in VHDL.

The [ range ] field is used to determine the number of bits in the vector and the location of the most significant and least significant bits. The key word used to describe the range value in VHDL are: downto and to. The next lines present a declaration of an 8-bit vector using the keywords:

Conversion Type

When writing VHDL code, it is often necessary to do a data conversion. Two general methods to convert between data types are available. The first method is to cast the signal to the correct type. In this method, it is converted between the signed, unsigned and std_logic_vector.

The code below is an example demonstrating the syntax to cast signals or data.

The second way employs functions. This method is used to convert between the signed or unsigned types and the integer type. To use a suitable conversion function, it is needed to include either the numeric_std or the std_logicarith packages. These packages are available in the IEEE library.

Assigning Data Values

When assigning data to a vector type, VHDL uses quotation marks (“) instead of apostrophes. Also, it can specify to use a hexadecimal notation by adding an ‘x’ to the start of the data. This works if the number of bits is a factor of four. Using octal values can be done by adding an ‘o’ to the start of the data. This works only with VHDL-2008. The code below gives some examples of how to assign data to vector types in VHDL.

Because VHDL is similar to other programming languages, it allows variables. These are declared in the architecture declaration area.

• variable – receives a value that can be updated during running simulations
• signal – time-dependent size that maps to ports
• constant – receives a value that cannot be modfied during simulation

Example: In this example, several variables of each of the above types are declared and used in a small code combination:

VHDL has a set of operators that can be used in creating designs. Predefined operators:

Example 1: After declaring the variables, f is assigned the value between a and b using a binary operator. The binary operator “and” can be replaced with another binary operator according to the designer's need. This operation is performed after the delay; for this task, the timing operator “after” is used.

Example 2: Uses the timing operator “wait” to implement a breakpoint and wait for an event specified to happen:

Example 3: Uses different shift operators to make changes at a bit level.

Example 4: The combined use of several operators:

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Find a training course, vhdl-2008: easier to use.

Many of the enhancements in VHDL-2008 are intended to make VHDL easier to use. These are all fairly minor additions to the language or changes to the syntax. Nevertheless, they will make a real difference in day-to-day VHDL design.

New condition operator, ??

• Enhanced bit string literals
• Hierarchical names

Vectors in aggregates

• Conditional and selected sequential statements
• Extensions to generate
• Simplified sensitivity lists

Arithmetic on std_logic_vector

How many times have you wanted to write something like this:

where A and B are STD_LOGIC ? You haven’t been able to, because VHDL’s if statement requires a boolean expression, not a STD_LOGIC one. You have to write this instead:

VHDL-2008 introduces a new operator, ?? . It ’s called the condition operator and it converts a STD_LOGIC expression to a BOOLEAN one: '1'  and 'H' are considered TRUE and everything else FALSE . (It also converts BIT to BOOLEAN ) So you can now write this:

or, even better ...

In certain circumstances, ?? is applied implicitly. The condition expression of an if statement is one of those. So you can indeed now write:

Enhanced bit string literals.

You use string literals as literal values of type STD_LOGIC_VECTOR or similar. For example,

In VHDL-1987, string literals provided, in effect, a way of expressing a vector as a binary number. VHDL-1993 introduced binary, octal and hexadecimal bit string literals :

One limitation in VHDL-1993 is that hexadecimal bit-string literals always contain a multiple of 4 bits, and octal ones a multiple of 3 bits. You can’t have a 10-bit hexadecimal bit-string literal, or one containing values other than 0, 1 or _, for example.

In VHDL-2008, bit string literals are enhanced:

• they may have an explicit width,
• they may be declared as signed or unsigned,
• they may include meta-values ('U', 'X', etc.)

Here are some examples:

Note that within bit string literals it is allowed to use either upper or lower case letters, i.e. F or f.

Hierarchical names.

Some of the new features in VHDL-2008 are intended for verification only, not for design. Verification engineers often want to write self-checking test environments. In VHDL this can be difficult as there is no easy way to access a signal or variable buried inside the design hierarchy from the top level of the verification environment.

VHDL-2008 addresses this by introducing external names . An external name may refer to a (shared) variable, signal, or constant which is in another part of the design hierarchy. External names are embedded in double angle brackets << >>

Special characters may be used to move up the hierarchy ^ and to root the path in a package @ . Some examples:

Other uses for external names include injecting errors from a test environment, and forcing and releasing values (see later).

VHDL aggregates allow a value to be made up from a collection individual array or record elements. For arrays, VHDL up to 1076-2002 allows syntax like this:

VHDL-2008 allows the use of a slice in an array aggregate. So for instance the examples above could be written:

It is also possible to use aggregates as the target of an assignment, like this:

Conditional and selected sequential statements.

Historically there have been two styles of writing "decision" statements in VHDL - concurrent and sequential. And you had to get them correct - you could not use a conditional signal assignment such as...

in a process. VHDL-2008 relaxes this and allows a flip-flop to be modelled like this:

It is also permitted to use the selected signal assignment in a process:

Extensions to generate .

VHDL-2008 makes the generate statement much more flexible. It is now allowed to use else and elsif . Also there is a case version of generate .

This makes generate easier to use. Instead of writing

you can write case...generate :

or you can write if...elsif...else generate :

Note that within each branch, you can still declare local names which will not clash with names in the other branches (such as label c1 above). It is still possible to declare local objects within the branch using begin-end .

The when others and else generate branches can be empty (do nothing) or may contain statements like the other branches.

Simplified sensitivity lists.

The keyword all may be used in the context of a sensitivity list, to mean that all signals read in the process should be added to the sensitivity list, for example:

This avoids a common problem where the author modifies a combination process and then forgets to update the sensitivity list, leading to a simulation/synthesis mis-match.

VHDL has a well-designed package IEEE.Numeric_Std which creates two new data types unsigned and signed . However it would sometimes be convenient to do arithmetic on std_logic_vector directly - treating it as either two's complement or unsigned.

In the past this has mainly been achieved by using the non-standard std_logic_unsigned and std_logic_signed packages . VHDL-2008 addresses this issue by adding two new standard arithmetic packages, IEEE.Numeric_Std_Unsigned and  IEEE.Numeric_Std_Signed .

Previous     Next

Go back to the main VHDL-2008 page.

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[SOLVED]   decimal numbers in vhdl

• Thread starter maia31
• Start date Aug 3, 2011
• Aug 3, 2011

Member level 1

When using std_logic_vectors(xx down to yy) I can use either binary numbers in the form "11010101" or hex numbers in the form x"00". How can I use decimal numbers?  

Advanced Member level 4

I guess you can use real datatype. SIGNAL A: real := 0.0; -- double  

ravics said: I guess you can use real datatype. SIGNAL A: real := 0.0; -- double Click to expand...

Full Member level 6

what about the function , conv_std_logic_vector?  

Full Member level 3

sometimes you can use as --***************************** entity decimal is Port ( clk : in STD_LOGIC; res : in STD_LOGIC; cnt : out STD_LOGIC_vector(0 to 5)); end decimal; architecture Behavioral of decimal is signal cnt_s : std_logic_vector(0 to 5); begin SM : process (Clk) begin if (Clk'event and Clk = '1') then if (Res = '1') then cnt_s <= "000000"; elsif cnt_s = 16 then --***************************** cnt_s <= "000000"; else cnt_s <= cnt_s + 4; --***************************** end if; end if; end process SM; cnt <= cnt_s; end Behavioral;  

well in define of constant constant8: std_logic_vector(15 downto 0) := 20000; the vhdl take error.:sad: what should i do????  

TrickyDicky

Advanced member level 7.

maia31 said: well in define of constant constant8: std_logic_vector(15 downto 0) := 20000; the vhdl take error.:sad: what should i do???? Click to expand...

signal a : integer range 0 to 1023 --limit to 10 bits signal a : integer range 1024 to 2047 --in some situations limit to 10 bits I hate Integer  

treqer said: signal a : integer range 0 to 1023 --limit to 10 bits signal a : integer range 1024 to 2047 --in some situations limit to 10 bits I hate Integer Click to expand...

• Aug 4, 2011

I do not use Integer if you want to then convert it into a bit signal, and work with individual bits.  

• Aug 6, 2011

treqer said: I do not use Integer if you want to then convert it into a bit signal, and work with individual bits. Click to expand...

I think you're getting very confused. Like I said, an integer is not a bit type. VHDL is strongly typed so has some strong rules, hence why you cannot assign an integer directly to a std_logic_vector. Also comparing VHDL to C# is not valid, as VHDL is not a programming language.  

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Assignment Symbol in VHDL

VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols:

Either of these assignment statements can be said out loud as the word “gets”. So for example in the assignment: test <= input_1; You could say out loud, “The signal test gets (assigned the value from) input_1.”

Note that there is an additional symbol used for component instantiations (=>) this is separate from an assignment.

Also note that <= is also a relational operator (less than or equal to). This is syntax dependent. If <= is used in any conditional statement (if, when, until) then it is a relational operator , otherwise it’s an assignment.

One other note about signal initialization: Signal initialization is allowed in most FPGA fabrics using the := VHDL assignment operator. It is good practice to assign all signals in an FPGA to a known-value when the FPGA is initialized. You should avoid using a reset signal to initialize your FPGA , instead use the := signal assignment.

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VHDL: Is there a convenient way to assign ascii values to std_logic_vector?

In verilog, I can assign a string to a vector like:

In VHDL, I'm having difficulty finding a method like this:

I've been using:

which is unclear and time consuming for large strings.

I've looked at the textio package and the txt_util package , but neither seem to be very clear on how to interpret a string and convert it to std_logic.

Is there a simple method of assigning ascii codes to std_logic in VHDL?

Here's a minimal example:

4 Answers 4

This one varies little for Morten's answer - it only uses one multiply, it copies the string instead of creating an alias, it uses an additional variable and it returns a standard logic vector with an ascending index range.

From a package called string_utils:

You could add an argument with a default specifying ascending/descending index range for the return value. You'd only need to provided the argument for the non default.

• Where is the package "string_utils" available? –  Morten Zilmer Commented Apr 7, 2014 at 10:45
• 1 @Morten www-eng.lbl.gov/~jmjoseph/for-JW/CIN-CFG-FPGA/… –  user1155120 Commented Apr 7, 2014 at 14:25

A small general function is one way to do it, with a suggestion below:

To return an ascii value of a character, use this code:

In your example you are trying to assign a string type to a std_logic_vector type. That is simply not allowed. VHDL is strongly typed.

SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0); ... hello <= "hello";

If your goal is to convert from hexa to ascii for printing simulation result you can simply do that:

character'val(to_integer(unsigned(my_std_logic_vector)))

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Assign binary in VHDL

I'm getting a syntax error near data0_sim in the following code - New to vhdl and confused as I think this should work:

• \$\begingroup\$ I'd suspect revealing just a bit more might be helpful. Constructing a simple testcase with an architecture declarative item for data0_sim and a concurrent signal assignment statement as shown yields no obvious errors, meaning more context appears needed. The actual error message might help, noting there can be errors that don't point to the character or line position where the actual syntax problem is found. \$\endgroup\$ –  user8352 Commented Sep 19, 2013 at 0:17

2 Answers 2

We can only guess since you haven't told us the syntax error, but from the code posted it MIGHT be:

Now there are two things you might be trying to do here:

1) declare a signal and give it an initial value. The correct syntax for that is:

Note that the initialiser uses the variable assignment syntax,to indicate that signal assignment semantics (postponed assignment, event generation) don't apply.

2) declare a signal and later, assign it a value.

The correct syntax for that requires more context : declarations and statements occupy two different spaces in a VHDL unit. This follows programming languages such as Ada, but it is rather different from C.

In VHDL, the context may be an entity/architecture such as:

• \$\begingroup\$ Note you can't always tell an object declaration from an interface declaration - "If no mode is explicitly given in an interface declaration other than an interface file declaration, mode in is assumed." The syntax error could be as simple as trying to assign something to a port formal with a missing mode out. Further, a last formal declaration in the port clause with a missing closing parenthesis on say a std_logic_vector range with a following entity declarative item (e.g. data0_sim) could cause interesting complaints. There's as yet not enough context to address a syntax error. \$\endgroup\$ –  user8352 Commented Sep 19, 2013 at 10:45
• \$\begingroup\$ Good points : my answer only covers some causes most likely to trip a beginner, not an exhaustive list. \$\endgroup\$ –  user16324 Commented Sep 19, 2013 at 10:52

Why don't you define a component, i.e.

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